// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*/
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/ {
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memory: memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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ramdisk: ramdisk {
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compatible = "rockchip,ramdisk";
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memory-region = <&ramdisk_r>;
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};
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reserved-memory {
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trust@0 {
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reg = <0x00000000 0x00200000>;
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no-map;
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};
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trust@200000 {
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reg = <0x00200000 0x00008000>;
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};
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ramoops@210000 {
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compatible = "ramoops";
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reg = <0x00210000 0x000f0000>;
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record-size = <0x20000>;
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console-size = <0x20000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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rtos@300000 {
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reg = <0x00300000 0x00100000>;
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no-map;
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};
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ramdisk_r: ramdisk@2800000 {
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reg = <0x02800000 (48 * 0x00100000)>;
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};
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ramdisk_c: ramdisk@5800000 {
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reg = <0x05800000 (20 * 0x00100000)>;
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};
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rkisp_thunderboot: rkisp@08000000 {
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reg = <0x08000000 (144 * 0x00100000)>;
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};
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};
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thunder_boot_rkisp: thunder-boot-rkisp {
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compatible = "rockchip,thunder-boot-rkisp";
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clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
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<&cru CLK_ISP>, <&cru CLK_MIPICSI_OUT>,
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<&cru CLK_I2C1>, <&cru PCLK_I2C1>,
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<&cru CLK_SCR1>, <&cru CLK_SCR1_CORE>,
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<&cru CLK_SCR1_RTC>, <&cru CLK_SCR1_JTAG>,
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<&cru PCLK_CSIPHY0>;
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clock-names = "aclk_isp", "hclk_isp",
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"clk_isp", "xvclk",
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"i2c1", "i2c1_pclk",
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"clk_scr1", "clk_scr1_core",
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"clk_scr1_rtc", "clk_scr1_jtag",
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"csiphy0_pclk";
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power-domains = <&power RV1126_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipicsi_clk0>;
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status = "okay";
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};
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};
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&cpu0_opp_table {
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rockchip,reboot-freq = <1200000>;
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/delete-node/ opp-1296000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-1512000000;
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};
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&cru {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-rates;
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/delete-property/ assigned-clock-parents;
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};
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&crypto {
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status = "okay";
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};
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&ddr_timing {
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status = "disabled";
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};
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&hw_decompress {
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status = "okay";
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memory-region = <&ramdisk_c>;
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};
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&isp_reserved {
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inactive;
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};
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&mtl_rx_setup {
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queue0 {
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status = "okay";
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};
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};
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&mtl_tx_setup {
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queue0 {
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status = "okay";
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};
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};
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&ramoops {
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status = "disabled";
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};
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&rkisp_vir0 {
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memory-region-thunderboot = <&rkisp_thunderboot>;
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};
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