// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
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*/
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/dts-v1/;
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#include "rv1109.dtsi"
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#include <dt-bindings/display/media-bus-format.h>
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/ {
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model = "Rockchip RV1109 FPGA Board";
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compatible = "rockchip,rv1109-fpga", "rockchip,rv1109";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 initrd=0x9000000,0xb05e7 init=/init";
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};
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panel: panel {
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compatible = "simple-panel";
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bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
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status = "okay";
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display-timings {
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native-mode = <&kd050fwfba002_timing>;
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kd050fwfba002_timing: timing0 {
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clock-frequency = <13500000>;
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hactive = <800>;
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vactive = <1280>;
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hback-porch = <24>;
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hfront-porch = <24>;
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vback-porch = <4>;
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vfront-porch = <2>;
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hsync-len = <16>;
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vsync-len = <2>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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port {
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panel_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_panel>;
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};
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};
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};
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};
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&display_subsystem {
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status = "okay";
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};
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&fiq_debugger {
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rockchip,baudrate = <115200>;
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status = "okay";
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};
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&mpp_srv {
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status = "okay";
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};
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&rgb {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgb_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in_rgb>;
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};
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};
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};
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};
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&rkvenc {
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status = "okay";
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};
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&rkvenc_mmu {
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status = "okay";
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};
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&uart2 {
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clocks = <&xin24m>, <&xin24m>;
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};
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&vop {
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status = "okay";
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};
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&vop_mmu {
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status = "okay";
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};
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