// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include "rv1106.dtsi"
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/ {
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compatible = "rockchip,rv1103";
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aliases {
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/delete-property/ gpio2;
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};
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};
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/delete-node/ &gpio2;
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&acodec {
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compatible = "rockchip,rv1103-codec";
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};
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&cpu0_opp_table {
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/delete-node/ opp-1200000000;
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/delete-node/ opp-1296000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-1512000000;
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/delete-node/ opp-1608000000;
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};
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&cru {
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assigned-clocks =
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru ARMCLK>,
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<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
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<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
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<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
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<&cru HCLK_PMU_ROOT>, <&cru CLK_339M_SRC>;
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assigned-clock-rates =
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<1188000000>, <1000000000>,
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<1104000000>,
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<400000000>, <200000000>,
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<100000000>, <300000000>,
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<100000000>, <100000000>,
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<200000000>, <264000000>;
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3m1_xfer>;
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3m1_xfer>;
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};
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&u2phy_otg {
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rockchip,vbus-always-on;
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};
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