// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "omap34xx.dtsi"
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#include "omap3-evm-common.dtsi"
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#include "omap3-evm-processor-common.dtsi"
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/ {
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model = "TI OMAP35XX EVM (TMDSEVM3530)";
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compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
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};
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&omap3_pmx_core2 {
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pinctrl-names = "default";
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pinctrl-0 = <&hsusb2_2_pins>;
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ehci_phy_pins: pinmux_ehci_phy_pins {
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pinctrl-single,pins = <
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/* EHCI PHY reset GPIO etk_d7.gpio_21 */
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OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
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/* EHCI VBUS etk_d8.gpio_22 */
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OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
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>;
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};
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/* Used by OHCI and EHCI. OHCI won't work without external phy */
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hsusb2_2_pins: pinmux_hsusb2_2_pins {
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pinctrl-single,pins = <
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/* etk_d10.hsusb2_clk */
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OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
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/* etk_d11.hsusb2_stp */
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OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
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/* etk_d12.hsusb2_dir */
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OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* etk_d13.hsusb2_nxt */
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OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* etk_d14.hsusb2_data0 */
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OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
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/* etk_d15.hsusb2_data1 */
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OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
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>;
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};
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};
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&gpmc {
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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linux,mtd-name= "micron,mt29f2g16abdhc";
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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ti,nand-ecc-opt = "bch8";
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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