// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
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*/
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#include "imx51.dtsi"
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/ {
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model = "Eukrea CPUIMX51";
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compatible = "eukrea,cpuimx51", "fsl,imx51";
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memory@90000000 {
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device_type = "memory";
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reg = <0x90000000 0x10000000>; /* 256M */
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pcf8563@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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tsc2007: tsc2007@49 {
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compatible = "ti,tsc2007";
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gpios = <&gpio4 0 1>;
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interrupt-parent = <&gpio4>;
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interrupts = <0x0 0x8>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc2007_1>;
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reg = <0x49>;
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ti,x-plate-ohms = <180>;
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};
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};
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&iomuxc {
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imx51-eukrea {
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pinctrl_tsc2007_1: tsc2007grp-1 {
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fsl,pins = <
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MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
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MX51_PAD_NANDF_D8__GPIO4_0 0x1f5
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
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MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
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MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
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MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
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MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
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MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
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MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
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MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
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MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
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MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
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MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
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MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
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MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
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MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
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MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
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MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
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MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX51_PAD_SD2_CMD__I2C1_SCL 0x400001ed
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MX51_PAD_SD2_CLK__I2C1_SDA 0x400001ed
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>;
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};
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};
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};
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&nfc {
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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