/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
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/* pmucru-clocks indices */
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/* pll clocks */
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#define PLL_GPLL 1
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/* sclk (special clocks) */
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#define CLK_OSC0_DIV32K 2
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#define CLK_RTC32K 3
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#define CLK_WIFI_DIV 4
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#define CLK_WIFI_OSC0 5
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#define CLK_WIFI 6
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#define CLK_PMU 7
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#define SCLK_UART1_DIV 8
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#define SCLK_UART1_FRACDIV 9
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#define SCLK_UART1_MUX 10
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#define SCLK_UART1 11
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#define CLK_I2C0 12
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#define CLK_I2C2 13
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#define CLK_CAPTURE_PWM0 14
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#define CLK_PWM0 15
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#define CLK_CAPTURE_PWM1 16
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#define CLK_PWM1 17
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#define CLK_SPI0 18
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#define DBCLK_GPIO0 19
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#define CLK_PMUPVTM 20
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#define CLK_CORE_PMUPVTM 21
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#define CLK_REF12M 22
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#define CLK_USBPHY_OTG_REF 23
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#define CLK_USBPHY_HOST_REF 24
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#define CLK_REF24M 25
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#define CLK_MIPIDSIPHY_REF 26
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/* pclk */
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#define PCLK_PDPMU 30
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#define PCLK_PMU 31
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#define PCLK_UART1 32
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#define PCLK_I2C0 33
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#define PCLK_I2C2 34
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#define PCLK_PWM0 35
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#define PCLK_PWM1 36
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#define PCLK_SPI0 37
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#define PCLK_GPIO0 38
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#define PCLK_PMUSGRF 39
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#define PCLK_PMUGRF 40
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#define PCLK_PMUCRU 41
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#define PCLK_CHIPVEROTP 42
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#define PCLK_PDPMU_NIU 43
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#define PCLK_PMUPVTM 44
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#define PCLK_SCRKEYGEN 45
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#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
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/* cru-clocks indices */
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/* pll clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_HPLL 4
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/* sclk (special clocks) */
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#define ARMCLK 5
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#define USB480M 6
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#define CLK_CORE_CPUPVTM 7
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#define CLK_CPUPVTM 8
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#define CLK_SCR1 9
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#define CLK_SCR1_CORE 10
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#define CLK_SCR1_RTC 11
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#define CLK_SCR1_JTAG 12
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#define SCLK_UART0_DIV 13
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#define SCLK_UART0_FRAC 14
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#define SCLK_UART0_MUX 15
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#define SCLK_UART0 16
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#define SCLK_UART2_DIV 17
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#define SCLK_UART2_FRAC 18
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#define SCLK_UART2_MUX 19
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#define SCLK_UART2 20
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#define SCLK_UART3_DIV 21
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#define SCLK_UART3_FRAC 22
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#define SCLK_UART3_MUX 23
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#define SCLK_UART3 24
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#define SCLK_UART4_DIV 25
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#define SCLK_UART4_FRAC 26
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#define SCLK_UART4_MUX 27
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#define SCLK_UART4 28
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#define SCLK_UART5_DIV 29
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#define SCLK_UART5_FRAC 30
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#define SCLK_UART5_MUX 31
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#define SCLK_UART5 32
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#define CLK_I2C1 33
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#define CLK_I2C3 34
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#define CLK_I2C4 35
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#define CLK_I2C5 36
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#define CLK_SPI1 37
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#define CLK_CAPTURE_PWM2 38
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#define CLK_PWM2 39
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#define DBCLK_GPIO1 40
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#define DBCLK_GPIO2 41
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#define DBCLK_GPIO3 42
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#define DBCLK_GPIO4 43
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#define CLK_SARADC 44
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#define CLK_TIMER0 45
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#define CLK_TIMER1 46
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#define CLK_TIMER2 47
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#define CLK_TIMER3 48
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#define CLK_TIMER4 49
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#define CLK_TIMER5 50
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#define CLK_CAN 51
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#define CLK_NPU_TSADC 52
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#define CLK_NPU_TSADCPHY 53
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#define CLK_CPU_TSADC 54
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#define CLK_CPU_TSADCPHY 55
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#define CLK_CRYPTO_CORE 56
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#define CLK_CRYPTO_PKA 57
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#define MCLK_I2S0_TX_DIV 58
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#define MCLK_I2S0_TX_FRACDIV 59
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#define MCLK_I2S0_TX_MUX 60
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#define MCLK_I2S0_TX 61
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#define MCLK_I2S0_RX_DIV 62
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#define MCLK_I2S0_RX_FRACDIV 63
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#define MCLK_I2S0_RX_MUX 64
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#define MCLK_I2S0_RX 65
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#define MCLK_I2S0_TX_OUT2IO 66
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#define MCLK_I2S0_RX_OUT2IO 67
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#define MCLK_I2S1_DIV 68
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#define MCLK_I2S1_FRACDIV 69
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#define MCLK_I2S1_MUX 70
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#define MCLK_I2S1 71
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#define MCLK_I2S1_OUT2IO 72
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#define MCLK_I2S2_DIV 73
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#define MCLK_I2S2_FRACDIV 74
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#define MCLK_I2S2_MUX 75
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#define MCLK_I2S2 76
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#define MCLK_I2S2_OUT2IO 77
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#define MCLK_PDM 78
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#define SCLK_ADUPWM_DIV 79
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#define SCLK_AUDPWM_FRACDIV 80
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#define SCLK_AUDPWM_MUX 81
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#define SCLK_AUDPWM 82
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#define CLK_ACDCDIG_ADC 83
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#define CLK_ACDCDIG_DAC 84
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#define CLK_ACDCDIG_I2C 85
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#define CLK_VENC_CORE 86
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#define CLK_VDEC_CORE 87
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#define CLK_VDEC_CA 88
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#define CLK_VDEC_HEVC_CA 89
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#define CLK_RGA_CORE 90
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#define CLK_IEP_CORE 91
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#define CLK_ISP_DIV 92
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#define CLK_ISP_NP5 93
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#define CLK_ISP_NUX 94
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#define CLK_ISP 95
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#define CLK_CIF_OUT_DIV 96
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#define CLK_CIF_OUT_FRACDIV 97
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#define CLK_CIF_OUT_MUX 98
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#define CLK_CIF_OUT 99
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#define CLK_MIPICSI_OUT_DIV 100
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#define CLK_MIPICSI_OUT_FRACDIV 101
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#define CLK_MIPICSI_OUT_MUX 102
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#define CLK_MIPICSI_OUT 103
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#define CLK_ISPP_DIV 104
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#define CLK_ISPP_NP5 105
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#define CLK_ISPP_NUX 106
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#define CLK_ISPP 107
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#define CLK_SDMMC 108
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#define SCLK_SDMMC_DRV 109
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#define SCLK_SDMMC_SAMPLE 110
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#define CLK_SDIO 111
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#define SCLK_SDIO_DRV 112
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#define SCLK_SDIO_SAMPLE 113
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#define CLK_EMMC 114
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#define SCLK_EMMC_DRV 115
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#define SCLK_EMMC_SAMPLE 116
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#define CLK_NANDC 117
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#define SCLK_SFC 118
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#define CLK_USBHOST_UTMI_OHCI 119
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#define CLK_USBOTG_REF 120
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#define CLK_GMAC_DIV 121
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#define CLK_GMAC_RGMII_M0 122
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#define CLK_GMAC_SRC_M0 123
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#define CLK_GMAC_RGMII_M1 124
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#define CLK_GMAC_SRC_M1 125
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#define CLK_GMAC_SRC 126
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#define CLK_GMAC_REF 127
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#define CLK_GMAC_TX_SRC 128
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#define CLK_GMAC_TX_DIV5 129
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#define CLK_GMAC_TX_DIV50 130
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#define RGMII_MODE_CLK 131
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#define CLK_GMAC_RX_SRC 132
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#define CLK_GMAC_RX_DIV2 133
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#define CLK_GMAC_RX_DIV20 134
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#define RMII_MODE_CLK 135
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#define CLK_GMAC_TX_RX 136
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#define CLK_GMAC_PTPREF 137
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#define CLK_GMAC_ETHERNET_OUT 138
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#define CLK_DDRPHY 139
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#define CLK_DDR_MON 140
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#define TMCLK_DDR_MON 141
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#define CLK_NPU_DIV 142
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#define CLK_NPU_NP5 143
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#define CLK_CORE_NPU 144
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#define CLK_CORE_NPUPVTM 145
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#define CLK_NPUPVTM 146
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#define SCLK_DDRCLK 147
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#define CLK_OTP 148
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/* dclk */
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#define DCLK_DECOM 150
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#define DCLK_VOP_DIV 151
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#define DCLK_VOP_FRACDIV 152
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#define DCLK_VOP_MUX 153
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#define DCLK_VOP 154
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#define DCLK_CIF 155
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#define DCLK_CIFLITE 156
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/* aclk */
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#define ACLK_PDBUS 160
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#define ACLK_DMAC 161
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#define ACLK_DCF 162
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#define ACLK_SPINLOCK 163
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#define ACLK_DECOM 164
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#define ACLK_PDCRYPTO 165
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#define ACLK_CRYPTO 166
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#define ACLK_PDVEPU 167
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#define ACLK_VENC 168
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#define ACLK_PDVDEC 169
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#define ACLK_PDJPEG 170
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#define ACLK_VDEC 171
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#define ACLK_JPEG 172
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#define ACLK_PDVO 173
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#define ACLK_RGA 174
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#define ACLK_VOP 175
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#define ACLK_IEP 176
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#define ACLK_PDVI_DIV 177
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#define ACLK_PDVI_NP5 178
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#define ACLK_PDVI 179
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#define ACLK_ISP 180
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#define ACLK_CIF 181
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#define ACLK_CIFLITE 182
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#define ACLK_PDISPP_DIV 183
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#define ACLK_PDISPP_NP5 184
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#define ACLK_PDISPP 185
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#define ACLK_ISPP 186
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#define ACLK_PDPHP 187
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#define ACLK_PDUSB 188
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#define ACLK_USBOTG 189
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#define ACLK_PDGMAC 190
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#define ACLK_GMAC 191
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#define ACLK_PDNPU_DIV 192
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#define ACLK_PDNPU_NP5 193
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#define ACLK_PDNPU 194
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#define ACLK_NPU 195
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/* hclk */
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#define HCLK_PDCORE_NIU 200
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#define HCLK_PDUSB 201
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#define HCLK_PDCRYPTO 202
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#define HCLK_CRYPTO 203
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#define HCLK_PDAUDIO 204
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#define HCLK_I2S0 205
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#define HCLK_I2S1 206
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#define HCLK_I2S2 207
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#define HCLK_PDM 208
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#define HCLK_AUDPWM 209
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#define HCLK_PDVEPU 210
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#define HCLK_VENC 211
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#define HCLK_PDVDEC 212
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#define HCLK_PDJPEG 213
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#define HCLK_VDEC 214
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#define HCLK_JPEG 215
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#define HCLK_PDVO 216
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#define HCLK_RGA 217
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#define HCLK_VOP 218
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#define HCLK_IEP 219
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#define HCLK_PDVI 220
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#define HCLK_ISP 221
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#define HCLK_CIF 222
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#define HCLK_CIFLITE 223
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#define HCLK_PDISPP 224
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#define HCLK_ISPP 225
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#define HCLK_PDPHP 226
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#define HCLK_PDSDMMC 227
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#define HCLK_SDMMC 228
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#define HCLK_PDSDIO 229
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#define HCLK_SDIO 230
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#define HCLK_PDNVM 231
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#define HCLK_EMMC 232
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#define HCLK_NANDC 233
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#define HCLK_SFC 234
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#define HCLK_SFCXIP 235
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#define HCLK_PDBUS 236
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#define HCLK_USBHOST 237
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#define HCLK_USBHOST_ARB 238
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#define HCLK_PDNPU 239
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#define HCLK_NPU 240
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/* pclk */
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#define PCLK_CPUPVTM 245
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#define PCLK_PDBUS 246
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#define PCLK_DCF 247
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#define PCLK_WDT 248
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#define PCLK_MAILBOX 249
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#define PCLK_UART0 250
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#define PCLK_UART2 251
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#define PCLK_UART3 252
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#define PCLK_UART4 253
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#define PCLK_UART5 254
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#define PCLK_I2C1 255
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#define PCLK_I2C3 256
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#define PCLK_I2C4 257
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#define PCLK_I2C5 258
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#define PCLK_SPI1 259
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#define PCLK_PWM2 261
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#define PCLK_GPIO1 262
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#define PCLK_GPIO2 263
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#define PCLK_GPIO3 264
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#define PCLK_GPIO4 265
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#define PCLK_SARADC 266
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#define PCLK_TIMER 267
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#define PCLK_DECOM 268
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#define PCLK_CAN 269
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#define PCLK_NPU_TSADC 270
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#define PCLK_CPU_TSADC 271
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#define PCLK_ACDCDIG 272
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#define PCLK_PDVO 273
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#define PCLK_DSIHOST 274
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#define PCLK_PDVI 275
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#define PCLK_CSIHOST 276
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#define PCLK_PDGMAC 277
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#define PCLK_GMAC 278
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#define PCLK_PDDDR 279
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#define PCLK_DDR_MON 280
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#define PCLK_PDNPU 281
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#define PCLK_NPUPVTM 282
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#define PCLK_PDTOP 283
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#define PCLK_TOPCRU 284
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#define PCLK_TOPGRF 285
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#define PCLK_CPUEMADET 286
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#define PCLK_DDRPHY 287
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#define PCLK_DSIPHY 289
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#define PCLK_CSIPHY0 290
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#define PCLK_CSIPHY1 291
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#define PCLK_USBPHY_HOST 292
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#define PCLK_USBPHY_OTG 293
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#define PCLK_OTP 294
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#define CLK_NR_CLKS (PCLK_OTP + 1)
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/* pmu soft-reset indices */
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/* pmu_cru_softrst_con0 */
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#define SRST_PDPMU_NIU_P 0
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#define SRST_PMU_SGRF_P 1
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#define SRST_PMU_SGRF_REMAP_P 2
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#define SRST_I2C0_P 3
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#define SRST_I2C0 4
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#define SRST_I2C2_P 7
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#define SRST_I2C2 8
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#define SRST_UART1_P 9
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#define SRST_UART1 10
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#define SRST_PWM0_P 11
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#define SRST_PWM0 12
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#define SRST_PWM1_P 13
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#define SRST_PWM1 14
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#define SRST_DDR_FAIL_SAFE 15
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/* pmu_cru_softrst_con1 */
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#define SRST_GPIO0_P 17
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#define SRST_GPIO0_DB 18
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#define SRST_SPI0_P 19
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#define SRST_SPI0 20
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#define SRST_PMUGRF_P 21
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#define SRST_CHIPVEROTP_P 22
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#define SRST_PMUPVTM 24
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#define SRST_PMUPVTM_P 25
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#define SRST_PMUCRU_P 30
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/* soft-reset indices */
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/* cru_softrst_con0 */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_NL2 12
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#define SRST_CORE_NIU_A 13
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#define SRST_DBG_DAPLITE_P 14
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#define SRST_DAPLITE_P 15
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/* cru_softrst_con1 */
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#define SRST_PDBUS_NIU1_A 16
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#define SRST_PDBUS_NIU1_H 17
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#define SRST_PDBUS_NIU1_P 18
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#define SRST_PDBUS_NIU2_A 19
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#define SRST_PDBUS_NIU2_H 20
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#define SRST_PDBUS_NIU3_A 21
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#define SRST_PDBUS_NIU3_H 22
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#define SRST_PDBUS_HOLD_NIU1_A 23
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#define SRST_DBG_NIU_P 24
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#define SRST_PDCORE_NIIU_H 25
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#define SRST_MUC_NIU 26
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#define SRST_DCF_A 29
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#define SRST_DCF_P 30
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#define SRST_SYSTEM_SRAM_A 31
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/* cru_softrst_con2 */
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#define SRST_I2C1_P 32
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#define SRST_I2C1 33
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#define SRST_I2C3_P 34
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#define SRST_I2C3 35
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#define SRST_I2C4_P 36
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#define SRST_I2C4 37
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#define SRST_I2C5_P 38
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#define SRST_I2C5 39
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#define SRST_SPI1_P 40
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#define SRST_SPI1 41
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#define SRST_MCU_CORE 42
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#define SRST_PWM2_P 44
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#define SRST_PWM2 45
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#define SRST_SPINLOCK_A 46
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/* cru_softrst_con3 */
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#define SRST_UART0_P 48
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#define SRST_UART0 49
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#define SRST_UART2_P 50
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#define SRST_UART2 51
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#define SRST_UART3_P 52
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#define SRST_UART3 53
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#define SRST_UART4_P 54
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#define SRST_UART4 55
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#define SRST_UART5_P 56
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#define SRST_UART5 57
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#define SRST_WDT_P 58
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#define SRST_SARADC_P 59
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#define SRST_GRF_P 61
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#define SRST_TIMER_P 62
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#define SRST_MAILBOX_P 63
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/* cru_softrst_con4 */
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#define SRST_TIMER0 64
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#define SRST_TIMER1 65
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#define SRST_TIMER2 66
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#define SRST_TIMER3 67
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#define SRST_TIMER4 68
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#define SRST_TIMER5 69
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#define SRST_INTMUX_P 70
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#define SRST_GPIO1_P 72
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#define SRST_GPIO1_DB 73
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#define SRST_GPIO2_P 74
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#define SRST_GPIO2_DB 75
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#define SRST_GPIO3_P 76
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#define SRST_GPIO3_DB 77
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#define SRST_GPIO4_P 78
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#define SRST_GPIO4_DB 79
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/* cru_softrst_con5 */
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#define SRST_CAN_P 80
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#define SRST_CAN 81
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#define SRST_DECOM_A 85
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#define SRST_DECOM_P 86
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#define SRST_DECOM_D 87
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#define SRST_PDCRYPTO_NIU_A 88
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#define SRST_PDCRYPTO_NIU_H 89
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#define SRST_CRYPTO_A 90
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#define SRST_CRYPTO_H 91
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#define SRST_CRYPTO_CORE 92
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#define SRST_CRYPTO_PKA 93
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#define SRST_SGRF_P 95
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/* cru_softrst_con6 */
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#define SRST_PDAUDIO_NIU_H 96
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#define SRST_PDAUDIO_NIU_P 97
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#define SRST_I2S0_H 98
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#define SRST_I2S0_TX_M 99
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#define SRST_I2S0_RX_M 100
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#define SRST_I2S1_H 101
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#define SRST_I2S1_M 102
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#define SRST_I2S2_H 103
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#define SRST_I2S2_M 104
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#define SRST_PDM_H 105
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#define SRST_PDM_M 106
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#define SRST_AUDPWM_H 107
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#define SRST_AUDPWM 108
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#define SRST_ACDCDIG_P 109
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#define SRST_ACDCDIG 110
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/* cru_softrst_con7 */
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#define SRST_PDVEPU_NIU_A 112
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#define SRST_PDVEPU_NIU_H 113
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#define SRST_VENC_A 114
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#define SRST_VENC_H 115
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#define SRST_VENC_CORE 116
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#define SRST_PDVDEC_NIU_A 117
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#define SRST_PDVDEC_NIU_H 118
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#define SRST_VDEC_A 119
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#define SRST_VDEC_H 120
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#define SRST_VDEC_CORE 121
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#define SRST_VDEC_CA 122
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#define SRST_VDEC_HEVC_CA 123
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#define SRST_PDJPEG_NIU_A 124
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#define SRST_PDJPEG_NIU_H 125
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#define SRST_JPEG_A 126
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#define SRST_JPEG_H 127
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/* cru_softrst_con8 */
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#define SRST_PDVO_NIU_A 128
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#define SRST_PDVO_NIU_H 129
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#define SRST_PDVO_NIU_P 130
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#define SRST_RGA_A 131
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#define SRST_RGA_H 132
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#define SRST_RGA_CORE 133
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#define SRST_VOP_A 134
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#define SRST_VOP_H 135
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#define SRST_VOP_D 136
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#define SRST_TXBYTEHS_DSIHOST 137
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#define SRST_DSIHOST_P 138
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#define SRST_IEP_A 139
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#define SRST_IEP_H 140
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#define SRST_IEP_CORE 141
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#define SRST_ISP_RX_P 142
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/* cru_softrst_con9 */
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#define SRST_PDVI_NIU_A 144
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#define SRST_PDVI_NIU_H 145
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#define SRST_PDVI_NIU_P 146
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#define SRST_ISP 147
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#define SRST_CIF_A 148
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#define SRST_CIF_H 149
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#define SRST_CIF_D 150
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#define SRST_CIF_P 151
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#define SRST_CIF_I 152
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#define SRST_CIF_RX_P 153
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#define SRST_PDISPP_NIU_A 154
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#define SRST_PDISPP_NIU_H 155
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#define SRST_ISPP_A 156
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#define SRST_ISPP_H 157
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#define SRST_ISPP 158
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#define SRST_CSIHOST_P 159
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/* cru_softrst_con10 */
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#define SRST_PDPHPMID_NIU_A 160
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#define SRST_PDPHPMID_NIU_H 161
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#define SRST_PDNVM_NIU_H 163
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#define SRST_SDMMC_H 164
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#define SRST_SDIO_H 165
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#define SRST_EMMC_H 166
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#define SRST_SFC_H 167
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#define SRST_SFCXIP_H 168
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#define SRST_SFC 169
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#define SRST_NANDC_H 170
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#define SRST_NANDC 171
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#define SRST_PDSDMMC_H 173
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#define SRST_PDSDIO_H 174
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/* cru_softrst_con11 */
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#define SRST_PDUSB_NIU_A 176
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#define SRST_PDUSB_NIU_H 177
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#define SRST_USBHOST_H 178
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#define SRST_USBHOST_ARB_H 179
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#define SRST_USBHOST_UTMI 180
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#define SRST_USBOTG_A 181
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#define SRST_USBPHY_OTG_P 182
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#define SRST_USBPHY_HOST_P 183
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#define SRST_USBPHYPOR_OTG 184
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#define SRST_USBPHYPOR_HOST 185
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#define SRST_PDGMAC_NIU_A 188
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#define SRST_PDGMAC_NIU_P 189
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#define SRST_GMAC_A 190
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/* cru_softrst_con12 */
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#define SRST_DDR_DFICTL_P 193
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#define SRST_DDR_MON_P 194
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#define SRST_DDR_STANDBY_P 195
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#define SRST_DDR_GRF_P 196
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#define SRST_DDR_MSCH_P 197
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#define SRST_DDR_SPLIT_A 198
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#define SRST_DDR_MSCH 199
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#define SRST_DDR_DFICTL 202
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#define SRST_DDR_STANDBY 203
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#define SRST_NPUMCU_NIU 205
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#define SRST_DDRPHY_P 206
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#define SRST_DDRPHY 207
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/* cru_softrst_con13 */
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#define SRST_PDNPU_NIU_A 208
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#define SRST_PDNPU_NIU_H 209
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#define SRST_PDNPU_NIU_P 210
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#define SRST_NPU_A 211
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#define SRST_NPU_H 212
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#define SRST_NPU 213
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#define SRST_NPUPVTM_P 214
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#define SRST_NPUPVTM 215
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#define SRST_NPU_TSADC_P 216
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#define SRST_NPU_TSADC 217
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#define SRST_NPU_TSADCPHY 218
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#define SRST_CIFLITE_A 220
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#define SRST_CIFLITE_H 221
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#define SRST_CIFLITE_D 222
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#define SRST_CIFLITE_RX_P 223
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/* cru_softrst_con14 */
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#define SRST_TOPNIU_P 224
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#define SRST_TOPCRU_P 225
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#define SRST_TOPGRF_P 226
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#define SRST_CPUEMADET_P 227
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#define SRST_CSIPHY0_P 228
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#define SRST_CSIPHY1_P 229
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#define SRST_DSIPHY_P 230
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#define SRST_CPU_TSADC_P 232
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#define SRST_CPU_TSADC 233
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#define SRST_CPU_TSADCPHY 234
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#define SRST_CPUPVTM_P 235
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#define SRST_CPUPVTM 236
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#endif
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