/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define PLL_NPLL 5
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#define ARMCLK 6
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/* sclk gates (special clocks) */
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#define SCLK_GPU 64
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#define SCLK_SPI0 65
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#define SCLK_SPI1 66
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#define SCLK_SPI2 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO0 69
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#define SCLK_SDIO1 70
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#define SCLK_EMMC 71
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#define SCLK_TSADC 72
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#define SCLK_SARADC 73
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#define SCLK_PS2C 74
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#define SCLK_NANDC0 75
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#define SCLK_NANDC1 76
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_UART3 80
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#define SCLK_UART4 81
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#define SCLK_I2S0 82
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#define SCLK_SPDIF 83
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#define SCLK_SPDIF8CH 84
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_TIMER4 89
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#define SCLK_TIMER5 90
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#define SCLK_TIMER6 91
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#define SCLK_HSADC 92
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#define SCLK_OTGPHY0 93
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#define SCLK_OTGPHY1 94
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#define SCLK_OTGPHY2 95
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#define SCLK_OTG_ADP 96
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#define SCLK_HSICPHY480M 97
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#define SCLK_HSICPHY12M 98
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#define SCLK_MACREF 99
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#define SCLK_LCDC_PWM0 100
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#define SCLK_LCDC_PWM1 101
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#define SCLK_MAC_RX 102
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#define SCLK_MAC_TX 103
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#define SCLK_EDP_24M 104
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#define SCLK_EDP 105
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#define SCLK_RGA 106
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#define SCLK_ISP 107
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#define SCLK_ISP_JPE 108
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#define SCLK_HDMI_HDCP 109
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#define SCLK_HDMI_CEC 110
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#define SCLK_HEVC_CABAC 111
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#define SCLK_HEVC_CORE 112
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#define SCLK_I2S0_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO0_DRV 115
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#define SCLK_SDIO1_DRV 116
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO0_SAMPLE 119
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#define SCLK_SDIO1_SAMPLE 120
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_USBPHY480M_SRC 122
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#define SCLK_PVTM_CORE 123
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#define SCLK_PVTM_GPU 124
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#define SCLK_CRYPTO 125
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#define SCLK_MIPIDSI_24M 126
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#define SCLK_VIP_OUT 127
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#define SCLK_DDRCLK 128
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#define SCLK_I2S_SRC 129
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#define SCLK_TSPOUT 130
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#define SCLK_TSP 131
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#define SCLK_HSADC0_TSP 132
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#define SCLK_HSADC1_TSP 133
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#define SCLK_27M_TSP 134
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#define SCLK_MAC_PLL 150
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#define SCLK_MAC 151
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#define SCLK_MACREF_OUT 152
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#define SCLK_TESTOUT_SRC 153
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#define SCLK_TESTOUT 154
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#define DCLK_VOP0 190
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#define DCLK_VOP1 191
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/* aclk gates */
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#define ACLK_GPU 192
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#define ACLK_DMAC1 193
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#define ACLK_DMAC2 194
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#define ACLK_MMU 195
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#define ACLK_GMAC 196
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#define ACLK_VOP0 197
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#define ACLK_VOP1 198
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#define ACLK_CRYPTO 199
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#define ACLK_RGA 200
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#define ACLK_RGA_NIU 201
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#define ACLK_IEP 202
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#define ACLK_VIO0_NIU 203
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#define ACLK_VIP 204
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#define ACLK_ISP 205
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#define ACLK_VIO1_NIU 206
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#define ACLK_HEVC 207
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#define ACLK_VCODEC 208
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#define ACLK_CPU 209
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#define ACLK_PERI 210
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#define ACLK_VIO0 211
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#define ACLK_VIO1 212
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_GPIO4 324
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#define PCLK_GPIO5 325
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#define PCLK_GPIO6 326
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#define PCLK_GPIO7 327
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#define PCLK_GPIO8 328
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#define PCLK_GRF 329
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#define PCLK_SGRF 330
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#define PCLK_PMU 331
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
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#define PCLK_I2C4 336
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#define PCLK_I2C5 337
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#define PCLK_SPI0 338
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#define PCLK_SPI1 339
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#define PCLK_SPI2 340
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_UART3 344
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#define PCLK_UART4 345
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#define PCLK_TSADC 346
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#define PCLK_SARADC 347
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#define PCLK_SIM 348
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#define PCLK_GMAC 349
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#define PCLK_PWM 350
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#define PCLK_RKPWM 351
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#define PCLK_PS2C 352
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#define PCLK_TIMER 353
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#define PCLK_TZPC 354
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#define PCLK_EDP_CTRL 355
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#define PCLK_MIPI_DSI0 356
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#define PCLK_MIPI_DSI1 357
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#define PCLK_MIPI_CSI 358
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#define PCLK_LVDS_PHY 359
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#define PCLK_HDMI_CTRL 360
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#define PCLK_VIO2_H2P 361
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#define PCLK_CPU 362
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#define PCLK_PERI 363
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#define PCLK_DDRUPCTL0 364
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#define PCLK_PUBL0 365
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#define PCLK_DDRUPCTL1 366
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#define PCLK_PUBL1 367
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#define PCLK_WDT 368
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#define PCLK_EFUSE256 369
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#define PCLK_EFUSE1024 370
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#define PCLK_ISP_IN 371
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#define PCLK_VIP 372
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#define PCLK_VIP_IN 373
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#define PCLK_PD_ALIVE 374
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#define PCLK_PD_PMU 375
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/* hclk gates */
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#define HCLK_GPS 448
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#define HCLK_OTG0 449
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#define HCLK_USBHOST0 450
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#define HCLK_USBHOST1 451
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#define HCLK_HSIC 452
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#define HCLK_NANDC0 453
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#define HCLK_NANDC1 454
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#define HCLK_TSP 455
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#define HCLK_SDMMC 456
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#define HCLK_SDIO0 457
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#define HCLK_SDIO1 458
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#define HCLK_EMMC 459
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#define HCLK_HSADC 460
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#define HCLK_CRYPTO 461
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#define HCLK_I2S0 462
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#define HCLK_SPDIF 463
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#define HCLK_SPDIF8CH 464
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#define HCLK_VOP0 465
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#define HCLK_VOP1 466
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#define HCLK_ROM 467
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#define HCLK_IEP 468
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#define HCLK_ISP 469
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#define HCLK_RGA 470
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#define HCLK_VIO_AHB_ARBI 471
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#define HCLK_VIO_NIU 472
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#define HCLK_VIP 473
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#define HCLK_VIO2_H2P 474
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#define HCLK_HEVC 475
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#define HCLK_VCODEC 476
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#define HCLK_CPU 477
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#define HCLK_PERI 478
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#define HCLK_USB_PERI 479
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#define HCLK_VIO 480
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#define CLK_NR_CLKS (HCLK_VIO + 1)
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/* soft-reset indices */
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#define SRST_CORE0 0
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#define SRST_CORE1 1
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#define SRST_CORE2 2
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#define SRST_CORE3 3
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#define SRST_CORE0_PO 4
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#define SRST_CORE1_PO 5
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#define SRST_CORE2_PO 6
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#define SRST_CORE3_PO 7
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#define SRST_PDCORE_STRSYS 8
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#define SRST_PDBUS_STRSYS 9
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#define SRST_L2C 10
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#define SRST_TOPDBG 11
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#define SRST_CORE0_DBG 12
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#define SRST_CORE1_DBG 13
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#define SRST_CORE2_DBG 14
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#define SRST_CORE3_DBG 15
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#define SRST_PDBUG_AHB_ARBITOR 16
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#define SRST_EFUSE256 17
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#define SRST_DMAC1 18
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#define SRST_INTMEM 19
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#define SRST_ROM 20
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#define SRST_SPDIF8CH 21
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#define SRST_TIMER 22
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#define SRST_I2S0 23
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#define SRST_SPDIF 24
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#define SRST_TIMER0 25
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#define SRST_TIMER1 26
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#define SRST_TIMER2 27
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#define SRST_TIMER3 28
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#define SRST_TIMER4 29
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#define SRST_TIMER5 30
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#define SRST_EFUSE 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_GPIO4 36
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#define SRST_GPIO5 37
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#define SRST_GPIO6 38
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#define SRST_GPIO7 39
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#define SRST_GPIO8 40
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#define SRST_I2C0 42
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#define SRST_I2C1 43
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#define SRST_I2C2 44
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#define SRST_I2C3 45
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#define SRST_I2C4 46
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#define SRST_I2C5 47
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#define SRST_DWPWM 48
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#define SRST_MMC_PERI 49
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#define SRST_PERIPH_MMU 50
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#define SRST_DAP 51
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#define SRST_DAP_SYS 52
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#define SRST_TPIU 53
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#define SRST_PMU_APB 54
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#define SRST_GRF 55
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#define SRST_PMU 56
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#define SRST_PERIPH_AXI 57
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#define SRST_PERIPH_AHB 58
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#define SRST_PERIPH_APB 59
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#define SRST_PERIPH_NIU 60
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#define SRST_PDPERI_AHB_ARBI 61
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#define SRST_EMEM 62
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#define SRST_USB_PERI 63
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#define SRST_DMAC2 64
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#define SRST_MAC 66
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#define SRST_GPS 67
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#define SRST_RKPWM 69
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#define SRST_CCP 71
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#define SRST_USBHOST0 72
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#define SRST_HSIC 73
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#define SRST_HSIC_AUX 74
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#define SRST_HSIC_PHY 75
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#define SRST_HSADC 76
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#define SRST_NANDC0 77
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#define SRST_NANDC1 78
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#define SRST_TZPC 80
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#define SRST_SPI0 83
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#define SRST_SPI1 84
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#define SRST_SPI2 85
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#define SRST_SARADC 87
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#define SRST_PDALIVE_NIU 88
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#define SRST_PDPMU_INTMEM 89
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#define SRST_PDPMU_NIU 90
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#define SRST_SGRF 91
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#define SRST_VIO_ARBI 96
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#define SRST_RGA_NIU 97
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#define SRST_VIO0_NIU_AXI 98
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#define SRST_VIO_NIU_AHB 99
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#define SRST_LCDC0_AXI 100
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#define SRST_LCDC0_AHB 101
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#define SRST_LCDC0_DCLK 102
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#define SRST_VIO1_NIU_AXI 103
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#define SRST_VIP 104
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#define SRST_RGA_CORE 105
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#define SRST_IEP_AXI 106
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#define SRST_IEP_AHB 107
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#define SRST_RGA_AXI 108
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#define SRST_RGA_AHB 109
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#define SRST_ISP 110
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#define SRST_EDP 111
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#define SRST_VCODEC_AXI 112
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#define SRST_VCODEC_AHB 113
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#define SRST_VIO_H2P 114
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#define SRST_MIPIDSI0 115
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#define SRST_MIPIDSI1 116
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#define SRST_MIPICSI 117
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#define SRST_LVDS_PHY 118
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#define SRST_LVDS_CON 119
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#define SRST_GPU 120
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#define SRST_HDMI 121
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#define SRST_CORE_PVTM 124
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#define SRST_GPU_PVTM 125
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#define SRST_MMC0 128
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#define SRST_SDIO0 129
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#define SRST_SDIO1 130
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#define SRST_EMMC 131
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#define SRST_USBOTG_AHB 132
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#define SRST_USBOTG_PHY 133
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#define SRST_USBOTG_CON 134
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#define SRST_USBHOST0_AHB 135
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#define SRST_USBHOST0_PHY 136
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#define SRST_USBHOST0_CON 137
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#define SRST_USBHOST1_AHB 138
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#define SRST_USBHOST1_PHY 139
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#define SRST_USBHOST1_CON 140
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#define SRST_USB_ADP 141
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#define SRST_ACC_EFUSE 142
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#define SRST_CORESIGHT 144
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#define SRST_PD_CORE_AHB_NOC 145
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#define SRST_PD_CORE_APB_NOC 146
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#define SRST_PD_CORE_MP_AXI 147
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#define SRST_GIC 148
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#define SRST_LCDC_PWM0 149
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#define SRST_LCDC_PWM1 150
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#define SRST_VIO0_H2P_BRG 151
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#define SRST_VIO1_H2P_BRG 152
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#define SRST_RGA_H2P_BRG 153
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#define SRST_HEVC 154
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#define SRST_TSADC 159
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#define SRST_DDRPHY0 160
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#define SRST_DDRPHY0_APB 161
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#define SRST_DDRCTRL0 162
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#define SRST_DDRCTRL0_APB 163
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#define SRST_DDRPHY0_CTRL 164
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#define SRST_DDRPHY1 165
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#define SRST_DDRPHY1_APB 166
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#define SRST_DDRCTRL1 167
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#define SRST_DDRCTRL1_APB 168
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#define SRST_DDRPHY1_CTRL 169
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#define SRST_DDRMSCH0 170
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#define SRST_DDRMSCH1 171
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#define SRST_CRYPTO 174
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#define SRST_C2C_HOST 175
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#define SRST_LCDC1_AXI 176
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#define SRST_LCDC1_AHB 177
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#define SRST_LCDC1_DCLK 178
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#define SRST_UART0 179
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#define SRST_UART1 180
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#define SRST_UART2 181
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#define SRST_UART3 182
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#define SRST_UART4 183
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#define SRST_SIMC 186
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#define SRST_PS2C 187
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#define SRST_TSP 188
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#define SRST_TSP_CLKIN0 189
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#define SRST_TSP_CLKIN1 190
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#define SRST_TSP_27M 191
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