/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*/
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#ifndef __MFD_MT6397_REGISTERS_H__
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#define __MFD_MT6397_REGISTERS_H__
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/* PMIC Registers */
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#define MT6397_CID 0x0100
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#define MT6397_TOP_CKPDN 0x0102
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#define MT6397_TOP_CKPDN_SET 0x0104
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#define MT6397_TOP_CKPDN_CLR 0x0106
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#define MT6397_TOP_CKPDN2 0x0108
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#define MT6397_TOP_CKPDN2_SET 0x010A
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#define MT6397_TOP_CKPDN2_CLR 0x010C
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#define MT6397_TOP_GPIO_CKPDN 0x010E
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#define MT6397_TOP_RST_CON 0x0114
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#define MT6397_WRP_CKPDN 0x011A
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#define MT6397_WRP_RST_CON 0x0120
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#define MT6397_TOP_RST_MISC 0x0126
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#define MT6397_TOP_CKCON1 0x0128
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#define MT6397_TOP_CKCON2 0x012A
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#define MT6397_TOP_CKTST1 0x012C
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#define MT6397_TOP_CKTST2 0x012E
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#define MT6397_OC_DEG_EN 0x0130
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#define MT6397_OC_CTL0 0x0132
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#define MT6397_OC_CTL1 0x0134
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#define MT6397_OC_CTL2 0x0136
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#define MT6397_INT_RSV 0x0138
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#define MT6397_TEST_CON0 0x013A
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#define MT6397_TEST_CON1 0x013C
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#define MT6397_STATUS0 0x013E
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#define MT6397_STATUS1 0x0140
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#define MT6397_PGSTATUS 0x0142
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#define MT6397_CHRSTATUS 0x0144
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#define MT6397_OCSTATUS0 0x0146
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#define MT6397_OCSTATUS1 0x0148
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#define MT6397_OCSTATUS2 0x014A
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#define MT6397_HDMI_PAD_IE 0x014C
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#define MT6397_TEST_OUT_L 0x014E
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#define MT6397_TEST_OUT_H 0x0150
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#define MT6397_TDSEL_CON 0x0152
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#define MT6397_RDSEL_CON 0x0154
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#define MT6397_GPIO_SMT_CON0 0x0156
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#define MT6397_GPIO_SMT_CON1 0x0158
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#define MT6397_GPIO_SMT_CON2 0x015A
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#define MT6397_GPIO_SMT_CON3 0x015C
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#define MT6397_DRV_CON0 0x015E
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#define MT6397_DRV_CON1 0x0160
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#define MT6397_DRV_CON2 0x0162
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#define MT6397_DRV_CON3 0x0164
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#define MT6397_DRV_CON4 0x0166
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#define MT6397_DRV_CON5 0x0168
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#define MT6397_DRV_CON6 0x016A
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#define MT6397_DRV_CON7 0x016C
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#define MT6397_DRV_CON8 0x016E
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#define MT6397_DRV_CON9 0x0170
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#define MT6397_DRV_CON10 0x0172
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#define MT6397_DRV_CON11 0x0174
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#define MT6397_DRV_CON12 0x0176
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#define MT6397_INT_CON0 0x0178
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#define MT6397_INT_CON1 0x017E
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#define MT6397_INT_STATUS0 0x0184
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#define MT6397_INT_STATUS1 0x0186
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#define MT6397_FQMTR_CON0 0x0188
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#define MT6397_FQMTR_CON1 0x018A
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#define MT6397_FQMTR_CON2 0x018C
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#define MT6397_EFUSE_DOUT_0_15 0x01C4
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#define MT6397_EFUSE_DOUT_16_31 0x01C6
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#define MT6397_EFUSE_DOUT_32_47 0x01C8
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#define MT6397_EFUSE_DOUT_48_63 0x01CA
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#define MT6397_SPI_CON 0x01CC
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#define MT6397_TOP_CKPDN3 0x01CE
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#define MT6397_TOP_CKCON3 0x01D4
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#define MT6397_EFUSE_DOUT_64_79 0x01D6
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#define MT6397_EFUSE_DOUT_80_95 0x01D8
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#define MT6397_EFUSE_DOUT_96_111 0x01DA
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#define MT6397_EFUSE_DOUT_112_127 0x01DC
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#define MT6397_EFUSE_DOUT_128_143 0x01DE
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#define MT6397_EFUSE_DOUT_144_159 0x01E0
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#define MT6397_EFUSE_DOUT_160_175 0x01E2
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#define MT6397_EFUSE_DOUT_176_191 0x01E4
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#define MT6397_EFUSE_DOUT_192_207 0x01E6
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#define MT6397_EFUSE_DOUT_208_223 0x01E8
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#define MT6397_EFUSE_DOUT_224_239 0x01EA
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#define MT6397_EFUSE_DOUT_240_255 0x01EC
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#define MT6397_EFUSE_DOUT_256_271 0x01EE
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#define MT6397_EFUSE_DOUT_272_287 0x01F0
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#define MT6397_EFUSE_DOUT_288_300 0x01F2
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#define MT6397_EFUSE_DOUT_304_319 0x01F4
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#define MT6397_BUCK_CON0 0x0200
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#define MT6397_BUCK_CON1 0x0202
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#define MT6397_BUCK_CON2 0x0204
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#define MT6397_BUCK_CON3 0x0206
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#define MT6397_BUCK_CON4 0x0208
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#define MT6397_BUCK_CON5 0x020A
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#define MT6397_BUCK_CON6 0x020C
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#define MT6397_BUCK_CON7 0x020E
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#define MT6397_BUCK_CON8 0x0210
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#define MT6397_BUCK_CON9 0x0212
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#define MT6397_VCA15_CON0 0x0214
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#define MT6397_VCA15_CON1 0x0216
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#define MT6397_VCA15_CON2 0x0218
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#define MT6397_VCA15_CON3 0x021A
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#define MT6397_VCA15_CON4 0x021C
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#define MT6397_VCA15_CON5 0x021E
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#define MT6397_VCA15_CON6 0x0220
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#define MT6397_VCA15_CON7 0x0222
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#define MT6397_VCA15_CON8 0x0224
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#define MT6397_VCA15_CON9 0x0226
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#define MT6397_VCA15_CON10 0x0228
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#define MT6397_VCA15_CON11 0x022A
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#define MT6397_VCA15_CON12 0x022C
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#define MT6397_VCA15_CON13 0x022E
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#define MT6397_VCA15_CON14 0x0230
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#define MT6397_VCA15_CON15 0x0232
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#define MT6397_VCA15_CON16 0x0234
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#define MT6397_VCA15_CON17 0x0236
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#define MT6397_VCA15_CON18 0x0238
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#define MT6397_VSRMCA15_CON0 0x023A
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#define MT6397_VSRMCA15_CON1 0x023C
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#define MT6397_VSRMCA15_CON2 0x023E
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#define MT6397_VSRMCA15_CON3 0x0240
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#define MT6397_VSRMCA15_CON4 0x0242
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#define MT6397_VSRMCA15_CON5 0x0244
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#define MT6397_VSRMCA15_CON6 0x0246
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#define MT6397_VSRMCA15_CON7 0x0248
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#define MT6397_VSRMCA15_CON8 0x024A
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#define MT6397_VSRMCA15_CON9 0x024C
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#define MT6397_VSRMCA15_CON10 0x024E
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#define MT6397_VSRMCA15_CON11 0x0250
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#define MT6397_VSRMCA15_CON12 0x0252
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#define MT6397_VSRMCA15_CON13 0x0254
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#define MT6397_VSRMCA15_CON14 0x0256
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#define MT6397_VSRMCA15_CON15 0x0258
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#define MT6397_VSRMCA15_CON16 0x025A
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#define MT6397_VSRMCA15_CON17 0x025C
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#define MT6397_VSRMCA15_CON18 0x025E
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#define MT6397_VSRMCA15_CON19 0x0260
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#define MT6397_VSRMCA15_CON20 0x0262
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#define MT6397_VSRMCA15_CON21 0x0264
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#define MT6397_VCORE_CON0 0x0266
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#define MT6397_VCORE_CON1 0x0268
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#define MT6397_VCORE_CON2 0x026A
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#define MT6397_VCORE_CON3 0x026C
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#define MT6397_VCORE_CON4 0x026E
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#define MT6397_VCORE_CON5 0x0270
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#define MT6397_VCORE_CON6 0x0272
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#define MT6397_VCORE_CON7 0x0274
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#define MT6397_VCORE_CON8 0x0276
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#define MT6397_VCORE_CON9 0x0278
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#define MT6397_VCORE_CON10 0x027A
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#define MT6397_VCORE_CON11 0x027C
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#define MT6397_VCORE_CON12 0x027E
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#define MT6397_VCORE_CON13 0x0280
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#define MT6397_VCORE_CON14 0x0282
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#define MT6397_VCORE_CON15 0x0284
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#define MT6397_VCORE_CON16 0x0286
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#define MT6397_VCORE_CON17 0x0288
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#define MT6397_VCORE_CON18 0x028A
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#define MT6397_VGPU_CON0 0x028C
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#define MT6397_VGPU_CON1 0x028E
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#define MT6397_VGPU_CON2 0x0290
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#define MT6397_VGPU_CON3 0x0292
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#define MT6397_VGPU_CON4 0x0294
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#define MT6397_VGPU_CON5 0x0296
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#define MT6397_VGPU_CON6 0x0298
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#define MT6397_VGPU_CON7 0x029A
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#define MT6397_VGPU_CON8 0x029C
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#define MT6397_VGPU_CON9 0x029E
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#define MT6397_VGPU_CON10 0x02A0
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#define MT6397_VGPU_CON11 0x02A2
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#define MT6397_VGPU_CON12 0x02A4
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#define MT6397_VGPU_CON13 0x02A6
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#define MT6397_VGPU_CON14 0x02A8
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#define MT6397_VGPU_CON15 0x02AA
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#define MT6397_VGPU_CON16 0x02AC
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#define MT6397_VGPU_CON17 0x02AE
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#define MT6397_VGPU_CON18 0x02B0
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#define MT6397_VIO18_CON0 0x0300
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#define MT6397_VIO18_CON1 0x0302
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#define MT6397_VIO18_CON2 0x0304
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#define MT6397_VIO18_CON3 0x0306
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#define MT6397_VIO18_CON4 0x0308
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#define MT6397_VIO18_CON5 0x030A
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#define MT6397_VIO18_CON6 0x030C
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#define MT6397_VIO18_CON7 0x030E
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#define MT6397_VIO18_CON8 0x0310
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#define MT6397_VIO18_CON9 0x0312
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#define MT6397_VIO18_CON10 0x0314
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#define MT6397_VIO18_CON11 0x0316
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#define MT6397_VIO18_CON12 0x0318
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#define MT6397_VIO18_CON13 0x031A
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#define MT6397_VIO18_CON14 0x031C
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#define MT6397_VIO18_CON15 0x031E
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#define MT6397_VIO18_CON16 0x0320
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#define MT6397_VIO18_CON17 0x0322
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#define MT6397_VIO18_CON18 0x0324
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#define MT6397_VPCA7_CON0 0x0326
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#define MT6397_VPCA7_CON1 0x0328
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#define MT6397_VPCA7_CON2 0x032A
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#define MT6397_VPCA7_CON3 0x032C
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#define MT6397_VPCA7_CON4 0x032E
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#define MT6397_VPCA7_CON5 0x0330
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#define MT6397_VPCA7_CON6 0x0332
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#define MT6397_VPCA7_CON7 0x0334
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#define MT6397_VPCA7_CON8 0x0336
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#define MT6397_VPCA7_CON9 0x0338
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#define MT6397_VPCA7_CON10 0x033A
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#define MT6397_VPCA7_CON11 0x033C
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#define MT6397_VPCA7_CON12 0x033E
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#define MT6397_VPCA7_CON13 0x0340
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#define MT6397_VPCA7_CON14 0x0342
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#define MT6397_VPCA7_CON15 0x0344
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#define MT6397_VPCA7_CON16 0x0346
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#define MT6397_VPCA7_CON17 0x0348
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#define MT6397_VPCA7_CON18 0x034A
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#define MT6397_VSRMCA7_CON0 0x034C
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#define MT6397_VSRMCA7_CON1 0x034E
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#define MT6397_VSRMCA7_CON2 0x0350
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#define MT6397_VSRMCA7_CON3 0x0352
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#define MT6397_VSRMCA7_CON4 0x0354
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#define MT6397_VSRMCA7_CON5 0x0356
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#define MT6397_VSRMCA7_CON6 0x0358
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#define MT6397_VSRMCA7_CON7 0x035A
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#define MT6397_VSRMCA7_CON8 0x035C
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#define MT6397_VSRMCA7_CON9 0x035E
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#define MT6397_VSRMCA7_CON10 0x0360
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#define MT6397_VSRMCA7_CON11 0x0362
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#define MT6397_VSRMCA7_CON12 0x0364
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#define MT6397_VSRMCA7_CON13 0x0366
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#define MT6397_VSRMCA7_CON14 0x0368
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#define MT6397_VSRMCA7_CON15 0x036A
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#define MT6397_VSRMCA7_CON16 0x036C
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#define MT6397_VSRMCA7_CON17 0x036E
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#define MT6397_VSRMCA7_CON18 0x0370
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#define MT6397_VSRMCA7_CON19 0x0372
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#define MT6397_VSRMCA7_CON20 0x0374
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#define MT6397_VSRMCA7_CON21 0x0376
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#define MT6397_VDRM_CON0 0x0378
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#define MT6397_VDRM_CON1 0x037A
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#define MT6397_VDRM_CON2 0x037C
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#define MT6397_VDRM_CON3 0x037E
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#define MT6397_VDRM_CON4 0x0380
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#define MT6397_VDRM_CON5 0x0382
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#define MT6397_VDRM_CON6 0x0384
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#define MT6397_VDRM_CON7 0x0386
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#define MT6397_VDRM_CON8 0x0388
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#define MT6397_VDRM_CON9 0x038A
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#define MT6397_VDRM_CON10 0x038C
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#define MT6397_VDRM_CON11 0x038E
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#define MT6397_VDRM_CON12 0x0390
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#define MT6397_VDRM_CON13 0x0392
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#define MT6397_VDRM_CON14 0x0394
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#define MT6397_VDRM_CON15 0x0396
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#define MT6397_VDRM_CON16 0x0398
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#define MT6397_VDRM_CON17 0x039A
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#define MT6397_VDRM_CON18 0x039C
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#define MT6397_BUCK_K_CON0 0x039E
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#define MT6397_BUCK_K_CON1 0x03A0
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#define MT6397_ANALDO_CON0 0x0400
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#define MT6397_ANALDO_CON1 0x0402
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#define MT6397_ANALDO_CON2 0x0404
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#define MT6397_ANALDO_CON3 0x0406
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#define MT6397_ANALDO_CON4 0x0408
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#define MT6397_ANALDO_CON5 0x040A
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#define MT6397_ANALDO_CON6 0x040C
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#define MT6397_ANALDO_CON7 0x040E
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#define MT6397_DIGLDO_CON0 0x0410
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#define MT6397_DIGLDO_CON1 0x0412
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#define MT6397_DIGLDO_CON2 0x0414
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#define MT6397_DIGLDO_CON3 0x0416
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#define MT6397_DIGLDO_CON4 0x0418
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#define MT6397_DIGLDO_CON5 0x041A
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#define MT6397_DIGLDO_CON6 0x041C
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#define MT6397_DIGLDO_CON7 0x041E
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#define MT6397_DIGLDO_CON8 0x0420
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#define MT6397_DIGLDO_CON9 0x0422
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#define MT6397_DIGLDO_CON10 0x0424
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#define MT6397_DIGLDO_CON11 0x0426
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#define MT6397_DIGLDO_CON12 0x0428
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#define MT6397_DIGLDO_CON13 0x042A
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#define MT6397_DIGLDO_CON14 0x042C
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#define MT6397_DIGLDO_CON15 0x042E
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#define MT6397_DIGLDO_CON16 0x0430
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#define MT6397_DIGLDO_CON17 0x0432
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#define MT6397_DIGLDO_CON18 0x0434
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#define MT6397_DIGLDO_CON19 0x0436
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#define MT6397_DIGLDO_CON20 0x0438
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#define MT6397_DIGLDO_CON21 0x043A
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#define MT6397_DIGLDO_CON22 0x043C
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#define MT6397_DIGLDO_CON23 0x043E
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#define MT6397_DIGLDO_CON24 0x0440
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#define MT6397_DIGLDO_CON25 0x0442
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#define MT6397_DIGLDO_CON26 0x0444
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#define MT6397_DIGLDO_CON27 0x0446
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#define MT6397_DIGLDO_CON28 0x0448
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#define MT6397_DIGLDO_CON29 0x044A
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#define MT6397_DIGLDO_CON30 0x044C
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#define MT6397_DIGLDO_CON31 0x044E
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#define MT6397_DIGLDO_CON32 0x0450
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#define MT6397_DIGLDO_CON33 0x045A
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#define MT6397_SPK_CON0 0x0600
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#define MT6397_SPK_CON1 0x0602
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#define MT6397_SPK_CON2 0x0604
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#define MT6397_SPK_CON3 0x0606
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#define MT6397_SPK_CON4 0x0608
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#define MT6397_SPK_CON5 0x060A
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#define MT6397_SPK_CON6 0x060C
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#define MT6397_SPK_CON7 0x060E
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#define MT6397_SPK_CON8 0x0610
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#define MT6397_SPK_CON9 0x0612
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#define MT6397_SPK_CON10 0x0614
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#define MT6397_SPK_CON11 0x0616
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#define MT6397_AUDDAC_CON0 0x0700
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#define MT6397_AUDBUF_CFG0 0x0702
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#define MT6397_AUDBUF_CFG1 0x0704
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#define MT6397_AUDBUF_CFG2 0x0706
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#define MT6397_AUDBUF_CFG3 0x0708
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#define MT6397_AUDBUF_CFG4 0x070A
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#define MT6397_IBIASDIST_CFG0 0x070C
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#define MT6397_AUDACCDEPOP_CFG0 0x070E
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#define MT6397_AUD_IV_CFG0 0x0710
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#define MT6397_AUDCLKGEN_CFG0 0x0712
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#define MT6397_AUDLDO_CFG0 0x0714
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#define MT6397_AUDLDO_CFG1 0x0716
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#define MT6397_AUDNVREGGLB_CFG0 0x0718
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#define MT6397_AUD_NCP0 0x071A
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#define MT6397_AUDPREAMP_CON0 0x071C
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#define MT6397_AUDADC_CON0 0x071E
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#define MT6397_AUDADC_CON1 0x0720
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#define MT6397_AUDADC_CON2 0x0722
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#define MT6397_AUDADC_CON3 0x0724
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#define MT6397_AUDADC_CON4 0x0726
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#define MT6397_AUDADC_CON5 0x0728
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#define MT6397_AUDADC_CON6 0x072A
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#define MT6397_AUDDIGMI_CON0 0x072C
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#define MT6397_AUDLSBUF_CON0 0x072E
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#define MT6397_AUDLSBUF_CON1 0x0730
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#define MT6397_AUDENCSPARE_CON0 0x0732
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#define MT6397_AUDENCCLKSQ_CON0 0x0734
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#define MT6397_AUDPREAMPGAIN_CON0 0x0736
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#define MT6397_ZCD_CON0 0x0738
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#define MT6397_ZCD_CON1 0x073A
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#define MT6397_ZCD_CON2 0x073C
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#define MT6397_ZCD_CON3 0x073E
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#define MT6397_ZCD_CON4 0x0740
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#define MT6397_ZCD_CON5 0x0742
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#define MT6397_NCP_CLKDIV_CON0 0x0744
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#define MT6397_NCP_CLKDIV_CON1 0x0746
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#endif /* __MFD_MT6397_REGISTERS_H__ */
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