/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header file for the Ingenic JZ47xx TCU driver
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*/
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#ifndef __LINUX_MFD_INGENIC_TCU_H_
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#define __LINUX_MFD_INGENIC_TCU_H_
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#include <linux/bitops.h>
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#define TCU_REG_WDT_TDR 0x00
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#define TCU_REG_WDT_TCER 0x04
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#define TCU_REG_WDT_TCNT 0x08
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#define TCU_REG_WDT_TCSR 0x0c
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#define TCU_REG_TER 0x10
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#define TCU_REG_TESR 0x14
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#define TCU_REG_TECR 0x18
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#define TCU_REG_TSR 0x1c
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#define TCU_REG_TFR 0x20
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#define TCU_REG_TFSR 0x24
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#define TCU_REG_TFCR 0x28
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#define TCU_REG_TSSR 0x2c
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#define TCU_REG_TMR 0x30
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#define TCU_REG_TMSR 0x34
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#define TCU_REG_TMCR 0x38
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#define TCU_REG_TSCR 0x3c
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#define TCU_REG_TDFR0 0x40
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#define TCU_REG_TDHR0 0x44
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#define TCU_REG_TCNT0 0x48
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#define TCU_REG_TCSR0 0x4c
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#define TCU_REG_OST_DR 0xe0
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#define TCU_REG_OST_CNTL 0xe4
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#define TCU_REG_OST_CNTH 0xe8
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#define TCU_REG_OST_TCSR 0xec
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#define TCU_REG_TSTR 0xf0
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#define TCU_REG_TSTSR 0xf4
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#define TCU_REG_TSTCR 0xf8
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#define TCU_REG_OST_CNTHBUF 0xfc
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#define TCU_TCSR_RESERVED_BITS 0x3f
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#define TCU_TCSR_PARENT_CLOCK_MASK 0x07
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#define TCU_TCSR_PRESCALE_LSB 3
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#define TCU_TCSR_PRESCALE_MASK 0x38
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#define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown gracefully 1: abruptly */
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#define TCU_TCSR_PWM_INITL_HIGH BIT(8) /* Sets the initial output level */
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#define TCU_TCSR_PWM_EN BIT(7) /* PWM pin output enable */
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#define TCU_WDT_TCER_TCEN BIT(0) /* Watchdog timer enable */
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#define TCU_CHANNEL_STRIDE 0x10
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#define TCU_REG_TDFRc(c) (TCU_REG_TDFR0 + ((c) * TCU_CHANNEL_STRIDE))
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#define TCU_REG_TDHRc(c) (TCU_REG_TDHR0 + ((c) * TCU_CHANNEL_STRIDE))
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#define TCU_REG_TCNTc(c) (TCU_REG_TCNT0 + ((c) * TCU_CHANNEL_STRIDE))
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#define TCU_REG_TCSRc(c) (TCU_REG_TCSR0 + ((c) * TCU_CHANNEL_STRIDE))
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#endif /* __LINUX_MFD_INGENIC_TCU_H_ */
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