/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Author Karsten Keil <kkeil@novell.com>
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*
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* Basic declarations for the mISDN HW channels
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*
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* Copyright 2008 by Karsten Keil <kkeil@novell.com>
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*/
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#ifndef MISDNHW_H
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#define MISDNHW_H
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#include <linux/mISDNif.h>
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#include <linux/timer.h>
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/*
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* HW DEBUG 0xHHHHGGGG
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* H - hardware driver specific bits
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* G - for all drivers
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*/
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#define DEBUG_HW 0x00000001
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#define DEBUG_HW_OPEN 0x00000002
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#define DEBUG_HW_DCHANNEL 0x00000100
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#define DEBUG_HW_DFIFO 0x00000200
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#define DEBUG_HW_BCHANNEL 0x00001000
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#define DEBUG_HW_BFIFO 0x00002000
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#define MAX_DFRAME_LEN_L1 300
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#define MAX_MON_FRAME 32
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#define MAX_LOG_SPACE 2048
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#define MISDN_COPY_SIZE 32
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/* channel->Flags bit field */
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#define FLG_TX_BUSY 0 /* tx_buf in use */
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#define FLG_TX_NEXT 1 /* next_skb in use */
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#define FLG_L1_BUSY 2 /* L1 is permanent busy */
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#define FLG_L2_ACTIVATED 3 /* activated from L2 */
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#define FLG_OPEN 5 /* channel is in use */
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#define FLG_ACTIVE 6 /* channel is activated */
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#define FLG_BUSY_TIMER 7
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/* channel type */
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#define FLG_DCHANNEL 8 /* channel is D-channel */
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#define FLG_BCHANNEL 9 /* channel is B-channel */
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#define FLG_ECHANNEL 10 /* channel is E-channel */
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#define FLG_TRANSPARENT 12 /* channel use transparent data */
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#define FLG_HDLC 13 /* channel use hdlc data */
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#define FLG_L2DATA 14 /* channel use L2 DATA primitivs */
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#define FLG_ORIGIN 15 /* channel is on origin site */
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/* channel specific stuff */
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#define FLG_FILLEMPTY 16 /* fill fifo on first frame (empty) */
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/* arcofi specific */
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#define FLG_ARCOFI_TIMER 17
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#define FLG_ARCOFI_ERROR 18
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/* isar specific */
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#define FLG_INITIALIZED 17
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#define FLG_DLEETX 18
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#define FLG_LASTDLE 19
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#define FLG_FIRST 20
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#define FLG_LASTDATA 21
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#define FLG_NMD_DATA 22
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#define FLG_FTI_RUN 23
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#define FLG_LL_OK 24
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#define FLG_LL_CONN 25
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#define FLG_DTMFSEND 26
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#define FLG_TX_EMPTY 27
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/* stop sending received data upstream */
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#define FLG_RX_OFF 28
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/* workq events */
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#define FLG_RECVQUEUE 30
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#define FLG_PHCHANGE 31
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#define schedule_event(s, ev) do { \
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test_and_set_bit(ev, &((s)->Flags)); \
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schedule_work(&((s)->workq)); \
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} while (0)
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struct dchannel {
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struct mISDNdevice dev;
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u_long Flags;
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struct work_struct workq;
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void (*phfunc) (struct dchannel *);
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u_int state;
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void *l1;
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void *hw;
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int slot; /* multiport card channel slot */
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struct timer_list timer;
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/* receive data */
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struct sk_buff *rx_skb;
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int maxlen;
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/* send data */
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struct sk_buff_head squeue;
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struct sk_buff_head rqueue;
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struct sk_buff *tx_skb;
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int tx_idx;
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int debug;
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/* statistics */
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int err_crc;
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int err_tx;
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int err_rx;
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};
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typedef int (dchannel_l1callback)(struct dchannel *, u_int);
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extern int create_l1(struct dchannel *, dchannel_l1callback *);
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/* private L1 commands */
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#define INFO0 0x8002
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#define INFO1 0x8102
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#define INFO2 0x8202
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#define INFO3_P8 0x8302
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#define INFO3_P10 0x8402
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#define INFO4_P8 0x8502
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#define INFO4_P10 0x8602
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#define LOSTFRAMING 0x8702
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#define ANYSIGNAL 0x8802
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#define HW_POWERDOWN 0x8902
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#define HW_RESET_REQ 0x8a02
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#define HW_POWERUP_REQ 0x8b02
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#define HW_DEACT_REQ 0x8c02
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#define HW_ACTIVATE_REQ 0x8e02
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#define HW_D_NOBLOCKED 0x8f02
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#define HW_RESET_IND 0x9002
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#define HW_POWERUP_IND 0x9102
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#define HW_DEACT_IND 0x9202
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#define HW_ACTIVATE_IND 0x9302
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#define HW_DEACT_CNF 0x9402
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#define HW_TESTLOOP 0x9502
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#define HW_TESTRX_RAW 0x9602
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#define HW_TESTRX_HDLC 0x9702
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#define HW_TESTRX_OFF 0x9802
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#define HW_TIMER3_IND 0x9902
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#define HW_TIMER3_VALUE 0x9a00
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#define HW_TIMER3_VMASK 0x00FF
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struct layer1;
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extern int l1_event(struct layer1 *, u_int);
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#define MISDN_BCH_FILL_SIZE 4
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struct bchannel {
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struct mISDNchannel ch;
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int nr;
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u_long Flags;
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struct work_struct workq;
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u_int state;
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void *hw;
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int slot; /* multiport card channel slot */
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struct timer_list timer;
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/* receive data */
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u8 fill[MISDN_BCH_FILL_SIZE];
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struct sk_buff *rx_skb;
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unsigned short maxlen;
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unsigned short init_maxlen; /* initial value */
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unsigned short next_maxlen; /* pending value */
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unsigned short minlen; /* for transparent data */
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unsigned short init_minlen; /* initial value */
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unsigned short next_minlen; /* pending value */
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/* send data */
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struct sk_buff *next_skb;
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struct sk_buff *tx_skb;
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struct sk_buff_head rqueue;
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int rcount;
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int tx_idx;
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int debug;
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/* statistics */
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int err_crc;
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int err_tx;
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int err_rx;
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int dropcnt;
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};
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extern int mISDN_initdchannel(struct dchannel *, int, void *);
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extern int mISDN_initbchannel(struct bchannel *, unsigned short,
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unsigned short);
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extern int mISDN_freedchannel(struct dchannel *);
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extern void mISDN_clear_bchannel(struct bchannel *);
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extern void mISDN_freebchannel(struct bchannel *);
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extern int mISDN_ctrl_bchannel(struct bchannel *, struct mISDN_ctrl_req *);
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extern void queue_ch_frame(struct mISDNchannel *, u_int,
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int, struct sk_buff *);
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extern int dchannel_senddata(struct dchannel *, struct sk_buff *);
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extern int bchannel_senddata(struct bchannel *, struct sk_buff *);
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extern int bchannel_get_rxbuf(struct bchannel *, int);
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extern void recv_Dchannel(struct dchannel *);
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extern void recv_Echannel(struct dchannel *, struct dchannel *);
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extern void recv_Bchannel(struct bchannel *, unsigned int, bool);
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extern void recv_Dchannel_skb(struct dchannel *, struct sk_buff *);
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extern void recv_Bchannel_skb(struct bchannel *, struct sk_buff *);
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extern int get_next_bframe(struct bchannel *);
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extern int get_next_dframe(struct dchannel *);
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#endif
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