/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AMD CS5535/CS5536 definitions
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* Copyright (C) 2006 Advanced Micro Devices, Inc.
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* Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
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*/
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#ifndef _CS5535_H
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#define _CS5535_H
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#include <asm/msr.h>
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/* MSRs */
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#define MSR_GLIU_P2D_RO0 0x10000029
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#define MSR_LX_GLD_MSR_CONFIG 0x48002001
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#define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
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* sheet has the wrong value */
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#define MSR_GLCP_SYS_RSTPLL 0x4C000014
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#define MSR_GLCP_DOTPLL 0x4C000015
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#define MSR_LBAR_SMB 0x5140000B
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#define MSR_LBAR_GPIO 0x5140000C
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#define MSR_LBAR_MFGPT 0x5140000D
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#define MSR_LBAR_ACPI 0x5140000E
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#define MSR_LBAR_PMS 0x5140000F
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#define MSR_DIVIL_SOFT_RESET 0x51400017
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#define MSR_PIC_YSEL_LOW 0x51400020
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#define MSR_PIC_YSEL_HIGH 0x51400021
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#define MSR_PIC_ZSEL_LOW 0x51400022
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#define MSR_PIC_ZSEL_HIGH 0x51400023
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#define MSR_PIC_IRQM_LPC 0x51400025
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#define MSR_MFGPT_IRQ 0x51400028
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#define MSR_MFGPT_NR 0x51400029
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#define MSR_MFGPT_SETUP 0x5140002B
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#define MSR_RTC_DOMA_OFFSET 0x51400055
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#define MSR_RTC_MONA_OFFSET 0x51400056
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#define MSR_RTC_CEN_OFFSET 0x51400057
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#define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
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#define MSR_GX_GLD_MSR_CONFIG 0xC0002001
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#define MSR_GX_MSR_PADSEL 0xC0002011
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static inline int cs5535_pic_unreqz_select_high(unsigned int group,
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unsigned int irq)
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{
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uint32_t lo, hi;
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rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
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lo &= ~(0xF << (group * 4));
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lo |= (irq & 0xF) << (group * 4);
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wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
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return 0;
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}
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/* PIC registers */
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#define CS5536_PIC_INT_SEL1 0x4d0
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#define CS5536_PIC_INT_SEL2 0x4d1
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/* resource sizes */
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#define LBAR_GPIO_SIZE 0xFF
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#define LBAR_MFGPT_SIZE 0x40
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#define LBAR_ACPI_SIZE 0x40
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#define LBAR_PMS_SIZE 0x80
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/*
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* PMC registers (PMS block)
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* It is only safe to access these registers as dword accesses.
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* See CS5536 Specification Update erratas 17 & 18
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*/
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#define CS5536_PM_SCLK 0x10
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#define CS5536_PM_IN_SLPCTL 0x20
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#define CS5536_PM_WKXD 0x34
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#define CS5536_PM_WKD 0x30
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#define CS5536_PM_SSC 0x54
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/*
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* PM registers (ACPI block)
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* It is only safe to access these registers as dword accesses.
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* See CS5536 Specification Update erratas 17 & 18
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*/
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#define CS5536_PM1_STS 0x00
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#define CS5536_PM1_EN 0x02
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#define CS5536_PM1_CNT 0x08
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#define CS5536_PM_GPE0_STS 0x18
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#define CS5536_PM_GPE0_EN 0x1c
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/* CS5536_PM1_STS bits */
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#define CS5536_WAK_FLAG (1 << 15)
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#define CS5536_RTC_FLAG (1 << 10)
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#define CS5536_PWRBTN_FLAG (1 << 8)
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/* CS5536_PM1_EN bits */
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#define CS5536_PM_PWRBTN (1 << 8)
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#define CS5536_PM_RTC (1 << 10)
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/* CS5536_PM_GPE0_STS bits */
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#define CS5536_GPIOM7_PME_FLAG (1 << 31)
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#define CS5536_GPIOM6_PME_FLAG (1 << 30)
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/* CS5536_PM_GPE0_EN bits */
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#define CS5536_GPIOM7_PME_EN (1 << 31)
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#define CS5536_GPIOM6_PME_EN (1 << 30)
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/* VSA2 magic values */
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#define VSA_VRC_INDEX 0xAC1C
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#define VSA_VRC_DATA 0xAC1E
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#define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
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#define VSA_VR_SIGNATURE 0x0003
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#define VSA_VR_MEM_SIZE 0x0200
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#define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
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#define GSW_VSA_SIG 0x534d /* General Software signature */
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#include <linux/io.h>
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static inline int cs5535_has_vsa2(void)
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{
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static int has_vsa2 = -1;
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if (has_vsa2 == -1) {
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uint16_t val;
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/*
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* The VSA has virtual registers that we can query for a
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* signature.
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*/
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outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
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outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
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val = inw(VSA_VRC_DATA);
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has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
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}
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return has_vsa2;
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}
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/* GPIOs */
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#define GPIO_OUTPUT_VAL 0x00
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#define GPIO_OUTPUT_ENABLE 0x04
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#define GPIO_OUTPUT_OPEN_DRAIN 0x08
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#define GPIO_OUTPUT_INVERT 0x0C
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#define GPIO_OUTPUT_AUX1 0x10
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#define GPIO_OUTPUT_AUX2 0x14
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#define GPIO_PULL_UP 0x18
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#define GPIO_PULL_DOWN 0x1C
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#define GPIO_INPUT_ENABLE 0x20
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#define GPIO_INPUT_INVERT 0x24
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#define GPIO_INPUT_FILTER 0x28
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#define GPIO_INPUT_EVENT_COUNT 0x2C
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#define GPIO_READ_BACK 0x30
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#define GPIO_INPUT_AUX1 0x34
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#define GPIO_EVENTS_ENABLE 0x38
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#define GPIO_LOCK_ENABLE 0x3C
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#define GPIO_POSITIVE_EDGE_EN 0x40
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#define GPIO_NEGATIVE_EDGE_EN 0x44
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#define GPIO_POSITIVE_EDGE_STS 0x48
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#define GPIO_NEGATIVE_EDGE_STS 0x4C
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#define GPIO_FLTR7_AMOUNT 0xD8
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#define GPIO_MAP_X 0xE0
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#define GPIO_MAP_Y 0xE4
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#define GPIO_MAP_Z 0xE8
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#define GPIO_MAP_W 0xEC
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#define GPIO_FE7_SEL 0xF7
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void cs5535_gpio_set(unsigned offset, unsigned int reg);
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void cs5535_gpio_clear(unsigned offset, unsigned int reg);
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int cs5535_gpio_isset(unsigned offset, unsigned int reg);
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int cs5535_gpio_set_irq(unsigned group, unsigned irq);
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void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
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/* MFGPTs */
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#define MFGPT_MAX_TIMERS 8
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#define MFGPT_TIMER_ANY (-1)
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#define MFGPT_DOMAIN_WORKING 1
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#define MFGPT_DOMAIN_STANDBY 2
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#define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
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#define MFGPT_CMP1 0
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#define MFGPT_CMP2 1
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#define MFGPT_EVENT_IRQ 0
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#define MFGPT_EVENT_NMI 1
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#define MFGPT_EVENT_RESET 3
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#define MFGPT_REG_CMP1 0
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#define MFGPT_REG_CMP2 2
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#define MFGPT_REG_COUNTER 4
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#define MFGPT_REG_SETUP 6
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#define MFGPT_SETUP_CNTEN (1 << 15)
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#define MFGPT_SETUP_CMP2 (1 << 14)
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#define MFGPT_SETUP_CMP1 (1 << 13)
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#define MFGPT_SETUP_SETUP (1 << 12)
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#define MFGPT_SETUP_STOPEN (1 << 11)
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#define MFGPT_SETUP_EXTEN (1 << 10)
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#define MFGPT_SETUP_REVEN (1 << 5)
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#define MFGPT_SETUP_CLKSEL (1 << 4)
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struct cs5535_mfgpt_timer;
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extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
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uint16_t reg);
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extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
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uint16_t value);
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extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
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int event, int enable);
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extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
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int *irq, int enable);
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extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
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int domain);
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extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
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static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
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int cmp, int *irq)
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{
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return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
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}
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static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
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int cmp, int *irq)
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{
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return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
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}
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#endif
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