/* bnx2_fw.h: QLogic bnx2 network driver.
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*
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* Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
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* Copyright (c) 2014-2015 QLogic Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*/
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/* Initialized Values for the Completion Processor. */
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static const struct cpu_reg cpu_reg_com = {
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.mode = BNX2_COM_CPU_MODE,
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.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
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.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
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.state = BNX2_COM_CPU_STATE,
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.state_value_clear = 0xffffff,
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.gpr0 = BNX2_COM_CPU_REG_FILE,
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.evmask = BNX2_COM_CPU_EVENT_MASK,
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.pc = BNX2_COM_CPU_PROGRAM_COUNTER,
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.inst = BNX2_COM_CPU_INSTRUCTION,
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.bp = BNX2_COM_CPU_HW_BREAKPOINT,
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.spad_base = BNX2_COM_SCRATCH,
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.mips_view_base = 0x8000000,
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};
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/* Initialized Values the Command Processor. */
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static const struct cpu_reg cpu_reg_cp = {
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.mode = BNX2_CP_CPU_MODE,
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.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
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.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
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.state = BNX2_CP_CPU_STATE,
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.state_value_clear = 0xffffff,
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.gpr0 = BNX2_CP_CPU_REG_FILE,
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.evmask = BNX2_CP_CPU_EVENT_MASK,
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.pc = BNX2_CP_CPU_PROGRAM_COUNTER,
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.inst = BNX2_CP_CPU_INSTRUCTION,
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.bp = BNX2_CP_CPU_HW_BREAKPOINT,
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.spad_base = BNX2_CP_SCRATCH,
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.mips_view_base = 0x8000000,
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};
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/* Initialized Values for the RX Processor. */
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static const struct cpu_reg cpu_reg_rxp = {
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.mode = BNX2_RXP_CPU_MODE,
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.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
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.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
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.state = BNX2_RXP_CPU_STATE,
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.state_value_clear = 0xffffff,
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.gpr0 = BNX2_RXP_CPU_REG_FILE,
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.evmask = BNX2_RXP_CPU_EVENT_MASK,
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.pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
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.inst = BNX2_RXP_CPU_INSTRUCTION,
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.bp = BNX2_RXP_CPU_HW_BREAKPOINT,
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.spad_base = BNX2_RXP_SCRATCH,
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.mips_view_base = 0x8000000,
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};
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/* Initialized Values for the TX Patch-up Processor. */
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static const struct cpu_reg cpu_reg_tpat = {
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.mode = BNX2_TPAT_CPU_MODE,
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.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
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.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
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.state = BNX2_TPAT_CPU_STATE,
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.state_value_clear = 0xffffff,
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.gpr0 = BNX2_TPAT_CPU_REG_FILE,
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.evmask = BNX2_TPAT_CPU_EVENT_MASK,
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.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
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.inst = BNX2_TPAT_CPU_INSTRUCTION,
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.bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
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.spad_base = BNX2_TPAT_SCRATCH,
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.mips_view_base = 0x8000000,
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};
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/* Initialized Values for the TX Processor. */
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static const struct cpu_reg cpu_reg_txp = {
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.mode = BNX2_TXP_CPU_MODE,
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.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
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.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
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.state = BNX2_TXP_CPU_STATE,
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.state_value_clear = 0xffffff,
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.gpr0 = BNX2_TXP_CPU_REG_FILE,
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.evmask = BNX2_TXP_CPU_EVENT_MASK,
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.pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
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.inst = BNX2_TXP_CPU_INSTRUCTION,
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.bp = BNX2_TXP_CPU_HW_BREAKPOINT,
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.spad_base = BNX2_TXP_SCRATCH,
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.mips_view_base = 0x8000000,
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};
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