/******************************************************************************
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*
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* Copyright(c) 2015 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifdef CONFIG_MCC_MODE
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#ifndef _RTW_MCC_H_
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#define _RTW_MCC_H_
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#include <drv_types.h> /* PADAPTER */
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#define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0
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#define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1
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#define MCC_STATUS_NEED_MCC BIT2
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#define MCC_STATUS_DOING_MCC BIT3
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#define MCC_SWCH_FW_EARLY_TIME 10 /* ms */
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#define MCC_EXPIRE_TIME 50 /* ms */
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#define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */
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#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */
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#define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0
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#define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1
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/* Lower for stop, Higher for start */
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#define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0
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#define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1
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#define MCC_SETCMD_STATUS_START_CONNECT 0x80
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#define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81
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/*
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* depenad platform or customer requirement(TP unit:Mbps),
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* must be provided by PM or sales or product document
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* too large value means not to limit tx bytes (current for ap mode)
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* NOTE: following values ref from test results
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*/
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#define MCC_AP_BW20_TARGET_TX_TP (300)
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#define MCC_AP_BW40_TARGET_TX_TP (300)
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#define MCC_AP_BW80_TARGET_TX_TP (300)
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#define MCC_STA_BW20_TARGET_TX_TP (35)
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#define MCC_STA_BW40_TARGET_TX_TP (70)
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#define MCC_STA_BW80_TARGET_TX_TP (140)
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#define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */
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#define MAX_MCC_NUM 2
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#ifdef CONFIG_RTL8822C
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#define DBG_MCC_REG_NUM 3
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#else
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#define DBG_MCC_REG_NUM 4
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#endif
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#define DBG_MCC_RF_REG_NUM 1
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#define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop)
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#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc)
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#define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv))
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#define SET_MCC_EN_FLAG(adapter, flag)\
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do { \
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adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \
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} while (0)
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#define SET_MCC_DURATION(adapter, val)\
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do { \
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adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \
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} while (0)
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#define SET_MCC_RUNTIME_DURATION(adapter, flag)\
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do { \
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adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \
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} while (0)
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#define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\
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do { \
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adapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \
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} while (0)
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#ifdef CONFIG_MCC_PHYDM_OFFLOAD
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enum mcc_cfg_phydm_ops {
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MCC_CFG_PHYDM_OFFLOAD = 0,
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MCC_CFG_PHYDM_RF_CH,
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MCC_CFG_PHYDM_ADD_CLIENT,
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MCC_CFG_PHYDM_REMOVE_CLIENT,
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MCC_CFG_PHYDM_START,
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MCC_CFG_PHYDM_STOP,
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MCC_CFG_PHYDM_DUMP,
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MCC_CFG_PHYDM_MAX,
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};
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#endif
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enum rtw_mcc_cmd_id {
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MCC_CMD_WK_CID = 0,
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MCC_SET_DURATION_WK_CID,
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MCC_GET_DBG_REG_WK_CID,
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#ifdef CONFIG_MCC_PHYDM_OFFLOAD
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MCC_SET_PHYDM_OFFLOAD_WK_CID,
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#endif
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};
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/* Represent Channel Tx Null setting */
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enum mcc_channel_tx_null {
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MCC_ENABLE_TX_NULL = 0,
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MCC_DISABLE_TX_NULL = 1,
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};
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/* Represent C2H Report setting */
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enum mcc_c2h_report {
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MCC_C2H_REPORT_DISABLE = 0,
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MCC_C2H_REPORT_FAIL_STATUS = 1,
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MCC_C2H_REPORT_ALL_STATUS = 2,
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};
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/* Represent Channel Scan */
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enum mcc_channel_scan {
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MCC_CHIDX = 0,
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MCC_SCANCH_RSVD_LOC = 1,
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};
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/* Represent FW status report of channel switch */
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enum mcc_status_rpt {
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MCC_RPT_SUCCESS = 0,
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MCC_RPT_TXNULL_FAIL = 1,
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MCC_RPT_STOPMCC = 2,
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MCC_RPT_READY = 3,
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MCC_RPT_SWICH_CHANNEL_NOTIFY = 7,
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MCC_RPT_UPDATE_NOA_START_TIME = 8,
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MCC_RPT_TSF = 9,
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MCC_RPT_MAX,
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};
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enum mcc_role {
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MCC_ROLE_STA = 0,
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MCC_ROLE_AP = 1,
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MCC_ROLE_GC = 2,
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MCC_ROLE_GO = 3,
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MCC_ROLE_MAX,
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};
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struct mcc_iqk_backup {
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u16 TX_X;
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u16 TX_Y;
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u16 RX_X;
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u16 RX_Y;
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};
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enum mcc_duration_setting {
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MCC_DURATION_MAPPING = 0,
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MCC_DURATION_DIRECET = 1,
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};
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enum mcc_sched_mode {
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MCC_FAIR_SCHEDULE = 0,
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MCC_FAVOR_STA = 1,
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MCC_FAVOR_P2P = 2,
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};
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/* mcc data for adapter */
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struct mcc_adapter_priv {
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u8 order; /* FW document, softap/AP must be 0 */
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enum mcc_role role; /* MCC role(AP,STA,GO,GC) */
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u8 mcc_duration; /* channel stay period, UNIT:1TU */
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/* flow control */
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u8 mcc_tx_stop; /* check if tp stop or not */
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u8 mcc_tp_limit; /* check if tp limit or not */
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u32 mcc_target_tx_bytes_to_port; /* customer require */
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u32 mcc_tx_bytes_to_port; /* already tx to tx fifo (write port) */
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/* data from kernel to check if enqueue data or netif stop queue */
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u32 mcc_tp;
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u64 mcc_tx_bytes_from_kernel;
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u64 mcc_last_tx_bytes_from_kernel;
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/* Backup IQK value for MCC */
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struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH];
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/* mgmt queue macid to avoid RA issue */
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u8 mgmt_queue_macid;
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/* set macid bitmap to let fw know which macid should be tx pause */
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/* all interface share total 16 macid */
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u16 mcc_macid_bitmap;
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/* use for NoA start time (unit: mircoseconds) */
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u32 noa_start_time;
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u8 p2p_go_noa_ie[MAX_P2P_IE_LEN];
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u32 p2p_go_noa_ie_len;
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u64 tsf;
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#ifdef CONFIG_TDLS
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u8 backup_tdls_en;
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#endif /* CONFIG_TDLS */
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u8 null_early;
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u8 null_rty_num;
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};
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struct mcc_obj_priv {
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u8 en_mcc; /* enable MCC or not */
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u8 duration; /* store duration(%) from registry, for primary adapter */
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u8 interval;
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u8 start_time;
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u8 mcc_c2h_status;
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u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */
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u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */
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u8 mcc_tolerance_time; /* used for detect mcc switch channel success */
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u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */
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u8 mcc_status; /* mcc status stop or start .... */
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u8 policy_index;
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u8 mcc_stop_threshold;
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u8 current_order;
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u8 last_tsfdiff;
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systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */
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_mutex mcc_mutex;
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_lock mcc_lock;
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PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */
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struct submit_ctx mcc_sctx;
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struct submit_ctx mcc_tsf_req_sctx;
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_mutex mcc_tsf_req_mutex;
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u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */
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#ifdef CONFIG_MCC_MODE_V2
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u8 mcc_iqk_value_rsvd_page[3];
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#endif /* CONFIG_MCC_MODE_V2 */
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u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM];
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u8 enable_runtime_duration;
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/* for LG */
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u8 mchan_sched_mode;
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_mutex mcc_dbg_reg_mutex;
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u32 dbg_reg[DBG_MCC_REG_NUM];
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u32 dbg_reg_val[DBG_MCC_REG_NUM];
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u32 dbg_rf_reg[DBG_MCC_RF_REG_NUM];
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u32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH];
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u8 mcc_phydm_offload;
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};
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/* backup IQK val */
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void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter);
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/* check mcc status */
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u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status);
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/* set mcc status */
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void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status);
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/* clear mcc status */
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void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status);
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/* dl mcc rsvd page */
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u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index
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, u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num);
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/* handle C2H */
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void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf);
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/* switch channel successfully or not */
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void rtw_hal_mcc_sw_status_check(PADAPTER padapter);
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/* change some scan flags under site survey */
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u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset);
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/* record data kernel TX to driver to check MCC concurrent TX */
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void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len);
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/* record data to port to let driver do flow ctrl */
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void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len);
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/* check stop write port or not */
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u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter);
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u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter);
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u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter);
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u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped);
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u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter);
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u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter);
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u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow);
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void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj);
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void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
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u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg);
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void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode);
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u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len);
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void rtw_hal_dump_mcc_policy_table(void *sel);
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void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add);
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void rtw_hal_mcc_process_noa(PADAPTER padapter);
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void rtw_hal_mcc_parameter_init(PADAPTER padapter);
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u8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val);
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u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val);
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#ifdef CONFIG_MCC_PHYDM_OFFLOAD
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u8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue);
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#endif /* CONFIG_MCC_PHYDM_OFFLOAD */
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#endif /* _RTW_MCC_H_ */
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#endif /* CONFIG_MCC_MODE */
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