/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __INC_PHYDM_API_H_8822C__
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#define __INC_PHYDM_API_H_8822C__
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#if (RTL8822C_SUPPORT)
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/*2021.02.05: Let the auto_nbi_detect th be 0x1 due to technicolor issue*/
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#define PHY_CONFIG_VERSION_8822C "1.8.9"
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/*#define CONFIG_TXAGC_DEBUG_8822C*/
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#define INVALID_RF_DATA 0xffffffff
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#define INVALID_TXAGC_DATA 0xff
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#define L_BND_DEFAULT_8822C 0xd
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#define config_phydm_read_rf_check_8822c(data) ((data) != INVALID_RF_DATA)
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#define config_phydm_read_txagc_check_8822c(data) ((data) != INVALID_TXAGC_DATA)
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enum agc_tab_sel_8822c {
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OFDM_2G_BW40_8822C = 0,
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OFDM_5G_LOW_BAND_8822C = 1,
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OFDM_5G_MID_BAND_8822C = 2,
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OFDM_5G_HIGH_BAND_8822C = 3,
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CCK_BW40_8822C = 4,
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CCK_BW20_8822C = 5,
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OFDM_2G_BW20_8822C = 6
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};
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struct txagc_table_8822c {
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u8 ref_pow_cck[2];
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u8 ref_pow_ofdm[2];
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s8 diff_t[NUM_RATE_AC_2SS]; /*by rate differential table*/
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};
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struct tx_path_en_8822c {
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u8 tx_path_en_ofdm_1sts;
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u8 tx_path_en_ofdm_2sts;
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u8 tx_path_en_cck;
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boolean is_path_ctrl_by_bb_reg;
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boolean stop_path_div;
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};
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struct rx_path_en_8822c {
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u8 rx_path_en_ofdm;
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u8 rx_path_en_cck;
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};
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boolean phydm_chk_pkg_set_valid_8822c(struct dm_struct *dm,
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u8 ver_bb, u8 ver_rf);
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u32 config_phydm_read_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,
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u32 reg_addr, u32 bit_mask);
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boolean config_phydm_write_rf_reg_8822c(struct dm_struct *dm, enum rf_path path,
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u32 reg_addr, u32 bit_mask, u32 data);
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boolean phydm_write_txagc_1byte_8822c(struct dm_struct *dm, u32 pw_idx,
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u8 hw_rate);
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boolean config_phydm_write_txagc_ref_8822c(struct dm_struct *dm, u8 power_index,
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enum rf_path path,
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enum PDM_RATE_TYPE rate_type);
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boolean config_phydm_write_txagc_diff_8822c(struct dm_struct *dm,
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s8 power_index1, s8 power_index2,
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s8 power_index3, s8 power_index4,
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u8 hw_rate);
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#ifdef CONFIG_TXAGC_DEBUG_8822C
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void phydm_txagc_tab_buff_show_8822c(struct dm_struct *dm);
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#endif
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s8 config_phydm_read_txagc_diff_8822c(struct dm_struct *dm, u8 hw_rate);
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u8 config_phydm_read_txagc_8822c(struct dm_struct *dm, enum rf_path path,
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u8 hw_rate, enum PDM_RATE_TYPE rate_type);
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void phydm_get_tx_path_en_setting_8822c(struct dm_struct *dm,
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struct tx_path_en_8822c *path);
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void phydm_get_rx_path_en_setting_8822c(struct dm_struct *dm,
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struct rx_path_en_8822c *path);
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void phydm_config_tx_path_8822c(struct dm_struct *dm, enum bb_path tx_path_2ss,
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enum bb_path tx_path_sel_1ss,
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enum bb_path tx_path_sel_cck);
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boolean config_phydm_trx_mode_8822c(struct dm_struct *dm,
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enum bb_path tx_path_en,
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enum bb_path rx_path,
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enum bb_path tx_path_sel_1ss);
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boolean config_phydm_switch_band_8822c(struct dm_struct *dm, u8 central_ch);
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boolean config_phydm_switch_channel_8822c(struct dm_struct *dm, u8 central_ch);
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boolean config_phydm_switch_bandwidth_8822c(struct dm_struct *dm, u8 pri_ch,
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enum channel_width bw);
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boolean config_phydm_switch_channel_bw_8822c(struct dm_struct *dm,
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u8 central_ch, u8 primary_ch_idx,
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enum channel_width bandwidth);
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void phydm_i_only_setting_8822c(struct dm_struct *dm, boolean en_i_only,
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boolean en_before_cca);
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boolean phydm_1rcca_setting_8822c(struct dm_struct *dm, boolean en_1rcca);
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void phydm_invld_pkt_setting_8822c(struct dm_struct *dm, boolean en_invld_pkt);
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void phydm_cck_gi_bound_8822c(struct dm_struct *dm);
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void phydm_ch_smooth_setting_8822c(struct dm_struct *dm, boolean en_ch_smooth);
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u16 phydm_get_dis_dpd_by_rate_8822c(struct dm_struct *dm);
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void phydm_set_auto_nbi_8822c(struct dm_struct *dm, boolean en_auto_nbi);
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boolean config_phydm_parameter_init_8822c(struct dm_struct *dm,
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enum odm_parameter_init type);
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boolean phydm_chk_bb_state_idle_8822c(struct dm_struct *dm);
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u16 phydm_get_gpio_setting_by_rfe_ctrl_8822c(struct dm_struct *dm);
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#if CONFIG_POWERSAVING
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boolean phydm_8822c_lps(struct dm_struct *dm, boolean enable_lps);
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#endif /* #if CONFIG_POWERSAVING */
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void config_phydm_set_txagc_to_hw_8822c(struct dm_struct *dm);
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boolean config_phydm_write_txagc_8822c(struct dm_struct *dm, u32 power_index,
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enum rf_path path, u8 hw_rate);
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void phydm_set_txagc_by_table_8822c(struct dm_struct *dm,
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struct txagc_table_8822c *tab);
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void phydm_get_txagc_ref_and_diff_8822c(struct dm_struct *dm,
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u8 txagc_buff[2][NUM_RATE_AC_2SS],
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u16 length,
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struct txagc_table_8822c *tab);
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#endif /* RTL8822C_SUPPORT */
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#endif /* __INC_PHYDM_API_H_8822C__ */
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