/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __ODM_REGDEFINE11AC_H__
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#define __ODM_REGDEFINE11AC_H__
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/* @2 RF REG LIST */
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/* @2 BB REG LIST */
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/* PAGE 8 */
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#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
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#define ODM_REG_BB_RX_PATH_11AC 0x808
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#define ODM_REG_BB_TX_PATH_11AC 0x80c
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#define ODM_REG_BB_ATC_11AC 0x860
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#define ODM_REG_EDCCA_POWER_CAL 0x8dc
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#define ODM_REG_DBG_RPT_11AC 0x8fc
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/* PAGE 9 */
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#define ODM_REG_EDCCA_DOWN_OPT 0x900
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#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
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#define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
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#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
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#define ODM_REG_CCX_PERIOD_11AC 0x990
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#define ODM_REG_NHM_TH9_TH10_11AC 0x994
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#define ODM_REG_CLM_11AC 0x994
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#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
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#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
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#define ODM_REG_NHM_TH8_11AC 0x9a0
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#define ODM_REG_NHM_9E8_11AC 0x9e8
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#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
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/* PAGE A */
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#define ODM_REG_CCK_CCA_11AC 0xA0A
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#define ODM_REG_CCK_FA_RST_11AC 0xA2C
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#define ODM_REG_CCK_FA_11AC 0xA5C
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/* PAGE B */
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#define ODM_REG_RST_RPT_11AC 0xB58
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/* PAGE C */
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#define ODM_REG_TRMUX_11AC 0xC08
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#define ODM_REG_IGI_A_11AC 0xC50
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/* PAGE E */
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#define ODM_REG_IGI_B_11AC 0xE50
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#define ODM_REG_ANT_11AC_B 0xE08
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/* PAGE F */
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#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
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#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
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#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
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#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
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#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
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#define ODM_REG_OFDM_FA_11AC 0xF48
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#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC
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#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
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#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC
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#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0
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#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4
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#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8
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#define ODM_REG_RPT_11AC 0xfa0
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#define ODM_REG_CLM_RESULT_11AC 0xfa4
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#define ODM_REG_NHM_CNT_11AC 0xfa8
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#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
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#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
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#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
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/* PAGE 18 */
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#define ODM_REG_IGI_C_11AC 0x1850
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/* PAGE 1A */
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#define ODM_REG_IGI_D_11AC 0x1A50
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/* PAGE 1D */
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#define ODM_REG_IGI_11AC3 0x1D70
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/* @2 MAC REG LIST */
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#define ODM_REG_RESP_TX_11AC 0x6D8
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/* @DIG Related */
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#define ODM_BIT_IGI_11AC 0x0000007F
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#define ODM_BIT_IGI_B_11AC3 0x00007F00
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#define ODM_BIT_IGI_C_11AC3 0x007F0000
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#define ODM_BIT_IGI_D_11AC3 0x7F000000
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#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
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#define ODM_BIT_BB_RX_PATH_11AC 0xF
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#define ODM_BIT_BB_TX_PATH_11AC 0xF
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#define ODM_BIT_BB_ATC_11AC BIT(14)
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#endif
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