/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/*************************************************************
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* include files
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************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#ifdef PHYDM_PRIMARY_CCA
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void phydm_write_dynamic_cca(
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void *dm_void,
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u8 curr_mf_state
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
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if (pri_cca->mf_state == curr_mf_state)
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return;
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if (dm->support_ic_type & ODM_IC_11N_SERIES) {
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if (curr_mf_state == MF_USC_LSC) {
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odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC);
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/*@40M OFDM MF CCA threshold*/
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odm_set_bb_reg(dm, R_0xc84, 0xf0000000,
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pri_cca->cca_th_40m_bkp);
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} else {
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odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state);
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/*@40M OFDM MF CCA threshold*/
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odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0);
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}
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}
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pri_cca->mf_state = curr_mf_state;
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PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n",
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((curr_mf_state == MF_USC_LSC) ? "D" :
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((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state);
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}
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void phydm_primary_cca_reset(
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void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
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PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n");
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pri_cca->mf_state = 0xff;
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pri_cca->pre_bw = (enum channel_width)0xff;
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phydm_write_dynamic_cca(dm, MF_USC_LSC);
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}
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void phydm_primary_cca_11n(
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void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
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enum channel_width curr_bw = (enum channel_width)*dm->band_width;
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if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
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return;
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if (!dm->is_linked) {
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PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n");
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if (pri_cca->pri_cca_is_become_linked) {
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phydm_primary_cca_reset(dm);
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pri_cca->pri_cca_is_become_linked = dm->is_linked;
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}
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return;
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} else {
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if (!pri_cca->pri_cca_is_become_linked) {
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PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n");
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pri_cca->pri_cca_is_become_linked = dm->is_linked;
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}
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}
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if (curr_bw != pri_cca->pre_bw) {
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PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n");
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pri_cca->pre_bw = curr_bw;
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if (curr_bw == CHANNEL_WIDTH_40) {
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if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {
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/* Primary CH @ upper sideband*/
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PHYDM_DBG(dm, DBG_PRI_CCA,
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"BW40M, Primary CH at USB\n");
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phydm_write_dynamic_cca(dm, MF_USC);
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} else {
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/*Primary CH @ lower sideband*/
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PHYDM_DBG(dm, DBG_PRI_CCA,
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"BW40M, Primary CH at LSB\n");
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phydm_write_dynamic_cca(dm, MF_LSC);
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}
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} else {
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PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n");
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phydm_primary_cca_reset(dm);
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}
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}
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}
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boolean
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odm_dynamic_primary_cca_dup_rts(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
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return pri_cca->dup_rts_flag;
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}
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void phydm_primary_cca_init(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
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if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
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return;
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if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
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return;
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PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n");
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#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
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pri_cca->dup_rts_flag = 0;
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pri_cca->intf_flag = 0;
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pri_cca->intf_type = 0;
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pri_cca->monitor_flag = 0;
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pri_cca->pri_cca_flag = 0;
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pri_cca->ch_offset = 0;
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#endif
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pri_cca->mf_state = 0xff;
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pri_cca->pre_bw = (enum channel_width)0xff;
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pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000);
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}
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void phydm_primary_cca(void *dm_void)
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{
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#ifdef PHYDM_PRIMARY_CCA
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
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return;
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if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
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return;
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phydm_primary_cca_11n(dm);
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#endif
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}
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#endif
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