/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/*@************************************************************
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* include files
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************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#ifdef PHYDM_MP_SUPPORT
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
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u8 path)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_mp *mp = &dm->dm_mp_table;
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u8 start = RF_PATH_A, end = RF_PATH_A;
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u8 i = 0;
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u8 central_ch = 0;
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boolean is_2g_ch = false;
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switch (path) {
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case RF_PATH_A:
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case RF_PATH_B:
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case RF_PATH_C:
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case RF_PATH_D:
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start = path;
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end = path;
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break;
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case RF_PATH_AB:
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start = RF_PATH_A;
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end = RF_PATH_B;
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break;
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#if (defined(PHYDM_COMPILE_IC_4SS))
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case RF_PATH_AC:
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start = RF_PATH_A;
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end = RF_PATH_C;
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break;
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case RF_PATH_AD:
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start = RF_PATH_A;
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end = RF_PATH_D;
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break;
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case RF_PATH_BC:
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start = RF_PATH_B;
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end = RF_PATH_C;
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break;
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case RF_PATH_BD:
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start = RF_PATH_B;
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end = RF_PATH_D;
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break;
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case RF_PATH_CD:
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start = RF_PATH_C;
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end = RF_PATH_D;
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break;
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case RF_PATH_ABC:
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start = RF_PATH_A;
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end = RF_PATH_C;
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break;
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case RF_PATH_ABD:
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start = RF_PATH_A;
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end = RF_PATH_D;
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break;
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case RF_PATH_ACD:
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start = RF_PATH_A;
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end = RF_PATH_D;
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break;
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case RF_PATH_BCD:
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start = RF_PATH_B;
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end = RF_PATH_D;
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break;
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case RF_PATH_ABCD:
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start = RF_PATH_A;
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end = RF_PATH_D;
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break;
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#endif
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}
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central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
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is_2g_ch = (central_ch <= 14) ? true : false;
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if (is_single_tone) {
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/*Disable CCA*/
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if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
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if(!(dm->support_ic_type & ODM_RTL8723F)) {
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odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
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odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
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}
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}
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/*Disable CCK CCA*/
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if(dm->support_ic_type & ODM_RTL8723F)
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odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
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/*Disable OFDM CCA*/
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odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
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if (dm->support_ic_type & ODM_RTL8723F) {
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for (i = start; i <= end; i++) {
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odm_set_rf_reg(dm, i, RF_0x5, BIT(0), 0x0);
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mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
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/*Tx mode: RF0x00[19:16]=4'b0010 */
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odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
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/*Lowest RF gain index: RF_0x1[5:0] TX power*/
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mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
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odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
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/*RF LO enabled */
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odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
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}
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} else {
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for (i = start; i <= end; i++) {
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mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
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/*Tx mode: RF0x00[19:16]=4'b0010 */
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odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
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/*Lowest RF gain index: RF_0x0[4:0] = 0*/
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odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
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/*RF LO enabled */
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odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
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}
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}
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#if (RTL8814B_SUPPORT)
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if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
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mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
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dm, RF_SYN0, RF_0x0, RFREG_MASK);
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/*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
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config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
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0x1f, 0x0);
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/*RF LO enabled */
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config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
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BIT(1), 0x1);
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/*SYN1*/
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if (*dm->band_width == CHANNEL_WIDTH_80_80) {
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mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
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dm, RF_SYN1, RF_0x0,
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RFREG_MASK);
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config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
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RF_0x0, 0x1f,
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0x0);
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config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
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RF_0x58, BIT(1),
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0x1);
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}
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}
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#endif
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} else {
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/*Enable CCA*/
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if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
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if(!(dm->support_ic_type & ODM_RTL8723F)) {
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odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
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odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
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}
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}
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/*Enable CCK CCA*/
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if(dm->support_ic_type & ODM_RTL8723F)
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odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
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/*Enable OFDM CCA*/
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odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
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if(dm->support_ic_type & ODM_RTL8723F) {
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for (i = start; i <= end; i++) {
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odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
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odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
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/*RF LO disabled */
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odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
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odm_set_rf_reg(dm, i, RF_0x5, BIT(0), 0x1);
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}
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} else {
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for (i = start; i <= end; i++) {
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odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
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/*RF LO disabled */
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odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
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}
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}
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#if (RTL8814B_SUPPORT)
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if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
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config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
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RFREG_MASK,
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mp->rf0_syn[RF_SYN0]);
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config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
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BIT(1), 0x0);
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/*SYN1*/
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if (*dm->band_width == CHANNEL_WIDTH_80_80) {
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config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
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RF_0x0,
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RFREG_MASK,
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mp->rf0_syn[RF_SYN1]);
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config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
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RF_0x58, BIT(1),
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0x0);
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}
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}
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#endif
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}
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}
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void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
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u32 rate_index)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_mp *mp = &dm->dm_mp_table;
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if (is_carrier_supp) {
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if (phydm_is_cck_rate(dm, (u8)rate_index)) {
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/*if CCK block on? */
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if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
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odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
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if(dm->support_ic_type & ODM_RTL8723F){
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/* @Carrier suppress tx */
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odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
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/*turn off scramble setting */
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odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
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/*Set CCK Tx Test Rate, set TxRate to 2Mbps */
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odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
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/* BB and PMAC cont tx */
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odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
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odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
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/* TX CCK ON */
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odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
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odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
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}
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else {
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/*Turn Off All Test mode */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
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/*transmit mode */
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odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
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/*turn off scramble setting */
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odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
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/*Set CCK Tx Test Rate, set TxRate to 1Mbps */
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odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
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}
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}
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} else { /*Stop Carrier Suppression. */
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if (phydm_is_cck_rate(dm, (u8)rate_index)) {
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if(dm->support_ic_type & ODM_RTL8723F) {
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/* TX Stop */
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odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
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/* Clear BB cont tx */
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odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
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/* Clear PMAC cont tx */
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odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
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/* Clear TX Stop */
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odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
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/* normal mode */
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odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
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/* turn on scramble setting */
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odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
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}
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else {
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/*normal mode */
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odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
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/*turn on scramble setting */
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odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
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}
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/*BB Reset */
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
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}
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}
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}
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void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_mp *mp = &dm->dm_mp_table;
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if (is_single_carrier) {
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/*1. if OFDM block on? */
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if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
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odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
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if (dm->support_ic_type & ODM_RTL8723F) {
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/*3. turn on scramble setting */
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odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
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/*4. Turn On single carrier. */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
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}
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else {
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/*2. set CCK test mode off, set to CCK normal mode */
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odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
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/*3. turn on scramble setting */
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odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
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/*4. Turn On single carrier. */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
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}
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} else {
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/*Turn off all test modes. */
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odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
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/*Delay 10 ms */
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ODM_delay_ms(10);
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/*BB Reset*/
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
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odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
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}
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}
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void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_mp *mp = &dm->dm_mp_table;
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if (phydm_is_cck_rate(dm, (u8)rate_index))
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mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
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else
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mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
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}
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void phydm_mp_get_rx_ok_jgr3(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_mp *mp = &dm->dm_mp_table;
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u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
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u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
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if(dm->support_ic_type & ODM_RTL8723F)
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cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
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else
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cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
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ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
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ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
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vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
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if(dm->support_ic_type & ODM_RTL8723F)
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cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
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else
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cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
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ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
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ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
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vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
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mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
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mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
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mp->io_value = (u32)mp->rx_phy_ok_cnt;
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}
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#endif
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void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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phydm_set_crystal_cap(dm, crystal_cap);
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}
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void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
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}
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void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
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u32 rate_index)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
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}
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void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
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}
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void phydm_mp_reset_rx_counters_phy(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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phydm_reset_bb_hw_cnt(dm);
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}
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void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_mp_get_tx_ok_jgr3(dm, rate_index);
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}
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void phydm_mp_get_rx_ok(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
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phydm_mp_get_rx_ok_jgr3(dm);
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}
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#endif
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