/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDM_LNA_SAT_H__
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#define __PHYDM_LNA_SAT_H__
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#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
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/* @1 ============================================================
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* 1 Definition
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* 1 ============================================================
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*/
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#define LNA_SAT_VERSION "1.1"
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/*@LNA saturation check*/
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#define OFDM_AGC_TAB_0 0
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#define OFDM_AGC_TAB_2 2
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#define DIFF_RSSI_TO_IGI 10
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#define ONE_SEC_MS 1000
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#define LNA_CHK_PERIOD 100 /*@ms*/
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#define LNA_CHK_CNT 10 /*@checks per callback*/
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#define LNA_CHK_DUTY_CYCLE 5 /*@percentage*/
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#define DELTA_STD 2
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#define DELTA_MEAN 2
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#define SNR_STATISTIC_SHIFT 8
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#define SNR_RPT_MAX 256
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/* @1 ============================================================
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* 1 enumrate
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* 1 ============================================================
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*/
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enum lna_sat_timer_state {
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INIT_LNA_SAT_CHK_TIMMER,
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CANCEL_LNA_SAT_CHK_TIMMER,
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RELEASE_LNA_SAT_CHK_TIMMER
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};
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#ifdef PHYDM_LNA_SAT_CHK_TYPE2
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enum lna_sat_chk_type2_status {
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ORI_TABLE_MONITOR,
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ORI_TABLE_TRAINING,
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SAT_TABLE_MONITOR,
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SAT_TABLE_TRAINING,
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SAT_TABLE_TRY_FAIL,
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ORI_TABLE_TRY_FAIL
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};
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#endif
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enum lna_sat_type {
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LNA_SAT_WITH_PEAK_DET = 1, /*type1*/
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LNA_SAT_WITH_TRAIN = 2, /*type2*/
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};
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#ifdef PHYDM_HW_SWITCH_AGC_TAB
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enum lna_pd_th_level {
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LNA_PD_TH_LEVEL0 = 0,
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LNA_PD_TH_LEVEL1 = 1,
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LNA_PD_TH_LEVEL2 = 2,
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LNA_PD_TH_LEVEL3 = 3
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};
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enum agc_tab_switch_state {
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AGC_SWH_IDLE,
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AGC_SWH_CCK,
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AGC_SWH_OFDM
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};
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#endif
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/* @1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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struct phydm_lna_sat_t {
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#ifdef PHYDM_LNA_SAT_CHK_TYPE1
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u8 chk_cnt;
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u8 chk_duty_cycle;
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u32 chk_period;/*@ms*/
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boolean is_disable_lna_sat_chk;
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boolean dis_agc_table_swh;
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#endif
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#ifdef PHYDM_LNA_SAT_CHK_TYPE2
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u8 force_traget_macid;
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u32 snr_var_thd;
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u32 delta_snr_mean;
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u16 ori_table_try_fail_times;
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u16 cnt_lower_snr_statistic;
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u16 sat_table_monitor_times;
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u16 force_change_period;
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u8 is_snr_detail_en;
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u8 is_force_lna_sat_table;
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u8 lwr_snr_ratio_bit_shift;
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u8 cnt_snr_statistic;
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u16 snr_statistic_sqr[SNR_RPT_MAX];
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u8 snr_statistic[SNR_RPT_MAX];
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u8 is_sm_done;
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u8 is_snr_done;
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u32 cur_snr_var;
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u8 total_bit_shift;
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u8 total_cnt_snr;
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u32 cur_snr_mean;
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u8 cur_snr_var0;
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u32 cur_lower_snr_mean;
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u32 pre_snr_mean;
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u32 pre_snr_var;
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u32 pre_lower_snr_mean;
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u8 nxt_state;
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u8 pre_state;
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#endif
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enum lna_sat_type lna_sat_type;
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u32 sat_cnt_acc_patha;
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u32 sat_cnt_acc_pathb;
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#ifdef PHYDM_IC_ABOVE_3SS
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u32 sat_cnt_acc_pathc;
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#endif
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#ifdef PHYDM_IC_ABOVE_4SS
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u32 sat_cnt_acc_pathd;
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#endif
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u32 check_time;
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boolean pre_sat_status;
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boolean cur_sat_status;
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#ifdef PHYDM_HW_SWITCH_AGC_TAB
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boolean hw_swh_tab_on;
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enum odm_rf_band cur_rf_band;
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#endif
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struct phydm_timer_list phydm_lna_sat_chk_timer;
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u32 cur_timer_check_cnt;
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u32 pre_timer_check_cnt;
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};
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/* @1 ============================================================
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* 1 function prototype
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* 1 ============================================================
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*/
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void phydm_lna_sat_chk_init(void *dm_void);
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u8 phydm_get_ofdm_agc_tab(void *dm_void);
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void phydm_lna_sat_chk(void *dm_void);
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void phydm_lna_sat_chk_timers(void *dm_void, u8 state);
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#ifdef PHYDM_LNA_SAT_CHK_TYPE1
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#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
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void phydm_lna_sat_chk_bb_init(void *dm_void);
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void phydm_set_ofdm_agc_tab_path(void *dm_void,
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u8 tab_sel, enum rf_path path);
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u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);
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#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
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#endif
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#ifdef PHYDM_LNA_SAT_CHK_TYPE2
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void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);
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#endif
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void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_lna_sat_chk_watchdog(void *dm_void);
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void phydm_lna_sat_check_init(void *dm_void);
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#ifdef PHYDM_HW_SWITCH_AGC_TAB
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void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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#endif
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#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
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#endif
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