/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDM_CCK_PD_H__
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#define __PHYDM_CCK_PD_H__
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/* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/
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#define CCK_PD_VERSION "4.0"
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/*@
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* 1 ============================================================
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* 1 Definition
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* 1 ============================================================
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*/
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#define CCK_FA_MA_RESET 0xffffffff
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#define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/
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#define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/
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#define MAXVALID_CS_RATIO 0x1f
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/*@Run time flag of CCK_PD HW type*/
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#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
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ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
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ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
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ODM_RTL8195A | ODM_RTL8188F)
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#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
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ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
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#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
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/*@extend for different bw & path*/
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#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
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#define CCK_PD_IC_TYPE5 (ODM_RTL8723F) /*@extend for different CR*/
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/*@Compile time flag of CCK_PD HW type*/
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#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
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RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
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RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
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RTL8195A_SUPPORT || RTL8188F_SUPPORT)
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#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
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#endif
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#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
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RTL8710B_SUPPORT || RTL8195B_SUPPORT)
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#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
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#endif
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#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
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#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
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#endif
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
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#endif
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#if (RTL8723F_SUPPORT)
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#define PHYDM_COMPILE_CCKPD_TYPE5 /*@extend for different & path*/
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#endif
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/*@
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* 1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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*/
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enum cckpd_lv {
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CCK_PD_LV_INIT = 0xff,
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CCK_PD_LV_0 = 0,
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CCK_PD_LV_1 = 1,
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CCK_PD_LV_2 = 2,
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CCK_PD_LV_3 = 3,
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CCK_PD_LV_4 = 4,
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CCK_PD_LV_MAX = 5
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};
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enum cckpd_mode {
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CCK_BW20_1R = 0,
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CCK_BW20_2R = 1,
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CCK_BW20_3R = 2,
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CCK_BW20_4R = 3,
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CCK_BW40_1R = 4,
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CCK_BW40_2R = 5,
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CCK_BW40_3R = 6,
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CCK_BW40_4R = 7
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};
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enum dcc_mode {
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DCC_DIG = 0,
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DCC_CCK_PD = 1
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};
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enum phydm_cck_pd_trend {
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CCKPD_STABLE = 0,
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CCKPD_INCREASING = 1,
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CCKPD_DECREASING = 2
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};
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/*@
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* 1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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#ifdef PHYDM_SUPPORT_CCKPD
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#ifdef PHYDM_DCC_ENHANCE
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struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/
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boolean dcc_en;
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enum dcc_mode dcc_mode;
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u32 dig_execute_cnt;
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u8 dcc_ratio;
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};
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#endif
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struct phydm_cckpd_struct {
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u8 cckpd_hw_type;
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u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
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u32 cck_fa_ma;
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u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
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u8 pause_lv;
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u8 cck_n_rx;
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u16 cck_fa_th[2];
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enum channel_width cck_bw;
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enum cckpd_lv cck_pd_lv;
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#ifdef PHYDM_COMPILE_CCKPD_TYPE2
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u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
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u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/
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#endif
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#ifdef PHYDM_COMPILE_CCKPD_TYPE3
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/*Default value*/
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u8 cck_pd_20m_1r;
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u8 cck_pd_20m_2r;
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u8 cck_pd_40m_1r;
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u8 cck_pd_40m_2r;
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u8 cck_cs_ratio_20m_1r;
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u8 cck_cs_ratio_20m_2r;
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u8 cck_cs_ratio_40m_1r;
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u8 cck_cs_ratio_40m_2r;
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u8 cck_din_shift_opt;
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/*Current value*/
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u8 cur_cck_pd_20m_1r;
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u8 cur_cck_pd_20m_2r;
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u8 cur_cck_pd_40m_1r;
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u8 cur_cck_pd_40m_2r;
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u8 cur_cck_cs_ratio_20m_1r;
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u8 cur_cck_cs_ratio_20m_2r;
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u8 cur_cck_cs_ratio_40m_1r;
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u8 cur_cck_cs_ratio_40m_2r;
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#endif
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#ifdef PHYDM_COMPILE_CCKPD_TYPE4
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/*@[bw][nrx][0:PD/1:CS][lv]*/
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u8 cckpd_jgr3[2][4][2][CCK_PD_LV_MAX];
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#endif
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#ifdef PHYDM_COMPILE_CCKPD_TYPE5
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/*@[bw][nrx][0:PD/1:CS][lv]*/
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u8 cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
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#endif
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};
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#endif
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/*@
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* 1 ============================================================
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* 1 function prototype
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* 1 ============================================================
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*/
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void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
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void phydm_cck_pd_th(void *dm_void);
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void phydm_cck_pd_init(void *dm_void);
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#ifdef PHYDM_DCC_ENHANCE
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void phydm_cckpd_type4_dcc(void *dm_void);
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void phydm_dig_cckpd_coex(void *dm_void);
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void phydm_dig_cckpd_coex_init(void *dm_void);
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void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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#endif
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#endif
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