/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDM_API_H__
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#define __PHYDM_API_H__
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/* 2019.10.22 Add get/shift rxagc API for 8822C*/
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#define PHYDM_API_VERSION "2.3"
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/* @1 ============================================================
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* 1 Definition
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* 1 ============================================================
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*/
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#define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E)
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#define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\
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ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\
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ODM_RTL8188F)
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#define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C)
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#define CN_CNT_MAX 10 /*@max condition number threshold*/
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#define FUNC_ENABLE 1
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#define FUNC_DISABLE 2
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/*@NBI API------------------------------------*/
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#define NBI_128TONE 27 /*register table size*/
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#define NBI_256TONE 59 /*register table size*/
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#define NUM_START_CH_80M 7
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#define NUM_START_CH_40M 14
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#define CH_OFFSET_40M 2
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#define CH_OFFSET_80M 6
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#define FFT_128_TYPE 1
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#define FFT_256_TYPE 2
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#define FREQ_POSITIVE 1
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#define FREQ_NEGATIVE 2
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/*@------------------------------------------------*/
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enum phystat_rpt {
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PHY_PWDB = 0,
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PHY_EVM = 1,
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PHY_CFO = 2,
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PHY_RXSNR = 3,
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PHY_LGAIN = 4,
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PHY_HT_AAGC_GAIN = 5,
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};
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#ifndef PHYDM_COMMON_API_SUPPORT
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#define INVALID_RF_DATA 0xffffffff
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#define INVALID_TXAGC_DATA 0xff
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#endif
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/* @1 ============================================================
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* 1 structure
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* 1 ============================================================
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*/
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struct phydm_api_stuc {
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u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
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u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
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u8 tx_queue_bitmap; /*REG0x520[23:16]*/
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u8 ccktx_path;
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u8 pri_ch_idx;
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};
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/* @1 ============================================================
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* 1 enumeration
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* 1 ============================================================
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*/
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/* @1 ============================================================
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* 1 function prototype
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* 1 ============================================================
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*/
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enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc);
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void phydm_reset_bb_hw_cnt(void *dm_void);
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void phydm_dynamic_ant_weighting(void *dm_void);
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#ifdef DYN_ANT_WEIGHTING_SUPPORT
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void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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#endif
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void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
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void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path);
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void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
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void phydm_config_cck_rx_antenna_init(void *dm_void);
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void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path);
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void phydm_config_cck_tx_path(void *dm_void, enum bb_path path);
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void phydm_tx_2path(void *dm_void);
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void phydm_stop_3_wire(void *dm_void, u8 set_type);
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u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);
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void phydm_dis_cck_trx(void *dm_void, u8 set_type);
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void phydm_bw_fixed_enable(void *dm_void, u8 enable);
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void phydm_bw_fixed_setting(void *dm_void);
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void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);
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void phydm_nbi_enable(void *dm_void, u32 enable);
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u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
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u32 sec_ch);
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u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
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u32 sec_ch);
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void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_stop_ck320(void *dm_void, u8 enable);
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boolean
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phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
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boolean phydm_spur_case_mapping(void *dm_void);
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enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch);
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#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
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u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx);
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u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
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u32 f_intf, u32 sec_ch, u8 wgt);
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void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
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u8 wgt);
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u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
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u32 sec_ch, u8 path);
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void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
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u8 path);
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void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);
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u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
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enum rf_path ant_path);
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void phydm_user_position_for_sniffer(void *dm_void, u8 user_position);
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#endif
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#ifdef PHYDM_COMMON_API_SUPPORT
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void phydm_reset_txagc(void *dm_void);
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boolean
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phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
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boolean is_positive);
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boolean
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phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,
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u8 hw_rate, boolean is_single_rate);
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u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);
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#if (RTL8822C_SUPPORT)
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void phydm_shift_rxagc_table(void *dm_void, boolean shift_up, u8 shift);
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#endif
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boolean
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phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
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enum channel_width bandwidth);
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boolean
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phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
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enum bb_path tx_path_ctrl);
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#endif
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#ifdef PHYDM_COMMON_API_NOT_SUPPORT
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u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate);
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#endif
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#ifdef CONFIG_MCC_DM
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#ifdef DYN_ANT_WEIGHTING_SUPPORT
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void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
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#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
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void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
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u8 val0, u8 val1);
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u8 phydm_check(void *dm_void);
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void phydm_mcc_init(void *dm_void);
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void phydm_mcc_switch(void *dm_void);
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#endif /*#ifdef CONFIG_MCC_DM*/
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#endif
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