/******************************************************************************
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*
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* Copyright(c) 2017 - 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#include "halmac_pcie_8822c.h"
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#include "halmac_pwr_seq_8822c.h"
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#include "../halmac_init_88xx.h"
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#include "../halmac_common_88xx.h"
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#include "../halmac_pcie_88xx.h"
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#include "../halmac_88xx_cfg.h"
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#if (HALMAC_8822C_SUPPORT && HALMAC_PCIE_SUPPORT)
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/**
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* mac_pwr_switch_pcie_8822c() - switch mac power
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* @adapter : the adapter of halmac
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* @pwr : power state
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* Author : KaiYuan Chang
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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#define INTF_INTGRA_MINREF_V1 90
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#define INTF_INTGRA_HOSTREF_V1 100
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static struct halmac_pcie_cfgspc_param pcie_cfgspc_param_def = {
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0,
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0,
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HALMAC_DISABLE,
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HALMAC_ENABLE,
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HALMAC_ENABLE,
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HALMAC_ENABLE,
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HALMAC_IGNORE,
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HALMAC_CLKDLY_0,
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HALMAC_L0SDLY_7US,
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HALMAC_L1DLY_16US,
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};
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enum pcie_clkdly_hw {
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PCIE_CLKDLY_HW_0 = 0,
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PCIE_CLKDLY_HW_30US = 0x1,
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PCIE_CLKDLY_HW_50US = 0x2,
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PCIE_CLKDLY_HW_100US = 0x3,
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PCIE_CLKDLY_HW_150US = 0x4,
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PCIE_CLKDLY_HW_200US = 0x5
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};
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enum pcie_l1dly_hw {
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PCIE_L1DLY_HW_16US = 4,
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PCIE_L1DLY_HW_32US = 5,
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PCIE_L1DLY_HW_64US = 6,
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PCIE_L1DLY_HW_INFI = 7
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};
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enum pcie_l0sdly_hw {
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PCIE_L0SDLY_HW_1US = 0,
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PCIE_L0SDLY_HW_3US = 2,
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PCIE_L0SDLY_HW_5US = 4,
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PCIE_L0SDLY_HW_7US = 6
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};
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#define GET_PCIE_FUNC_STUS(val, mask) \
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((val & mask) ? HALMAC_ENABLE : HALMAC_DISABLE)
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static u16
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get_target(struct halmac_adapter *adapter);
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static enum halmac_ret_status
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pcie_cfgspc_write_8822c(struct halmac_adapter *adapter,
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struct halmac_pcie_cfgspc_param *param);
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static enum halmac_ret_status
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pcie_cfgspc_read_8822c(struct halmac_adapter *adapter,
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struct halmac_pcie_cfgspc_param *param);
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static void
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update_pcie_func_8822c(u8 *val, u8 bitmask, enum halmac_func_ctrl ctrl,
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enum halmac_func_ctrl def_ctrl);
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static u8
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chk_stus_l1ss_8822c(struct halmac_adapter *adapter);
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static enum halmac_ret_status
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update_clkdly_8822c(struct halmac_adapter *adapter, u8 *val,
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enum halmac_pcie_clkdly ctrl,
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enum halmac_pcie_clkdly def_ctrl);
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static enum halmac_ret_status
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update_pcie_clk_8822c(struct halmac_adapter *adapter, u8 *val);
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static enum halmac_ret_status
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update_aspmdly_8822c(struct halmac_adapter *adapter, u8 *val,
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struct halmac_pcie_cfgspc_param *param,
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struct halmac_pcie_cfgspc_param *param_def);
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enum halmac_ret_status
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mac_pwr_switch_pcie_8822c(struct halmac_adapter *adapter,
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enum halmac_mac_power pwr)
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{
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u8 value8;
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u8 rpwm;
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struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr);
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PLTFM_MSG_TRACE("[TRACE]8822C pwr seq ver = %s\n",
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HALMAC_8822C_PWR_SEQ_VER);
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adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);
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/* Check FW still exist or not */
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if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
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/* Leave 32K */
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rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
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HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);
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}
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value8 = HALMAC_REG_R8(REG_CR);
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if (value8 == 0xEA)
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adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
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else
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adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
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/* Check if power switch is needed */
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if (pwr == HALMAC_MAC_POWER_ON &&
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adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
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PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
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return HALMAC_RET_PWR_UNCHANGE;
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}
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if (pwr == HALMAC_MAC_POWER_OFF) {
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if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822c) !=
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HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
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return HALMAC_RET_POWER_OFF_FAIL;
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}
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adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
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adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
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init_adapter_dynamic_param_88xx(adapter);
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} else {
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if (pwr_seq_parser_88xx(adapter, card_en_flow_8822c) !=
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HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
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return HALMAC_RET_POWER_ON_FAIL;
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}
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adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
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}
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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return HALMAC_RET_SUCCESS;
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}
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/**
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* halmac_pcie_switch_8822c() - pcie gen1/gen2 switch
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* @adapter : the adapter of halmac
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* @cfg : gen1/gen2 selection
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* Author : KaiYuan Chang
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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pcie_switch_8822c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
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{
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u8 value8;
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u32 value32;
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u8 speed = 0;
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u32 cnt = 0;
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enum halmac_ret_status status;
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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if (cfg == HALMAC_PCIE_GEN1) {
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value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
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status = dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET,
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value8 | BIT(0));
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if (status != HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]DBI write 8 bits fail!\n");
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return status;
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}
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value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
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status = dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET,
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value32 | BIT(17));
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if (status != HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]DBI write 32 bits fail!\n");
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return status;
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}
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speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
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cnt = 2000;
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while ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) {
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PLTFM_DELAY_US(50);
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speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
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speed &= 0x0F;
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cnt--;
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}
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if (speed != PCIE_GEN1_SPEED) {
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PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
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return HALMAC_RET_FAIL;
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}
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} else if (cfg == HALMAC_PCIE_GEN2) {
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value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
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status = dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET,
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value8 | BIT(1));
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if (status != HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]DBI write 8 bits fail!\n");
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return status;
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}
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value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
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status = dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET,
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value32 | BIT(17));
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if (status != HALMAC_RET_SUCCESS) {
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PLTFM_MSG_ERR("[ERR]DBI write 32 bits fail!\n");
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return status;
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}
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speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
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cnt = 2000;
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while ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) {
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PLTFM_DELAY_US(50);
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speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
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speed &= 0x0F;
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cnt--;
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}
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if (speed != PCIE_GEN2_SPEED) {
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PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
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return HALMAC_RET_FAIL;
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}
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} else {
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PLTFM_MSG_ERR("[ERR]Error Speed !\n");
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return HALMAC_RET_FAIL;
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}
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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return HALMAC_RET_SUCCESS;
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}
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/**
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* phy_cfg_pcie_8822c() - phy config
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* @adapter : the adapter of halmac
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* Author : KaiYuan Chang
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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phy_cfg_pcie_8822c(struct halmac_adapter *adapter,
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enum halmac_intf_phy_platform pltfm)
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{
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enum halmac_ret_status status = HALMAC_RET_SUCCESS;
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PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
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status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822c, pltfm,
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HAL_INTF_PHY_PCIE_GEN1);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822c, pltfm,
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HAL_INTF_PHY_PCIE_GEN2);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
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return HALMAC_RET_SUCCESS;
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}
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/**
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* intf_tun_pcie_8822c() - pcie interface fine tuning
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* @adapter : the adapter of halmac
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* Author : Rick Liu
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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intf_tun_pcie_8822c(struct halmac_adapter *adapter)
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{
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return HALMAC_RET_SUCCESS;
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}
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/**
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* cfgspc_set_pcie_8822c() - pcie configuration space setting
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* @adapter : the adapter of halmac
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* Author : Rick Liu
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* Return : enum halmac_ret_status
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* More details of status code can be found in prototype document
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*/
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enum halmac_ret_status
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cfgspc_set_pcie_8822c(struct halmac_adapter *adapter,
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struct halmac_pcie_cfgspc_param *param)
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{
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enum halmac_ret_status status = HALMAC_RET_SUCCESS;
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if (param->write == 1)
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status = pcie_cfgspc_write_8822c(adapter, param);
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if (param->read == 1)
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status = pcie_cfgspc_read_8822c(adapter, param);
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return status;
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}
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static enum halmac_ret_status
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pcie_cfgspc_write_8822c(struct halmac_adapter *adapter,
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struct halmac_pcie_cfgspc_param *param)
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{
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u8 l1_val;
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u8 aspm_val;
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u8 l1ss_val;
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u8 clk_val;
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struct halmac_pcie_cfgspc_param *param_def = &pcie_cfgspc_param_def;
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enum halmac_ret_status status;
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l1_val = dbi_r8_88xx(adapter, PCIE_L1_CTRL);
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aspm_val = dbi_r8_88xx(adapter, PCIE_ASPM_CTRL);
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l1ss_val = dbi_r8_88xx(adapter, PCIE_L1SS_CTRL);
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clk_val = dbi_r8_88xx(adapter, PCIE_CLK_CTRL);
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if (l1_val == 0xFF || aspm_val == 0xFF || l1ss_val == 0xFF ||
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clk_val == 0xFF) {
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PLTFM_MSG_ERR("[ERR] PCIE CFG reg read 0xFF!\n");
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return HALMAC_RET_FAIL;
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}
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update_pcie_func_8822c(&aspm_val, PCIE_BIT_L0S,
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param->l0s_ctrl, param_def->l0s_ctrl);
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status = update_pcie_clk_8822c(adapter, &l1_val);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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update_pcie_func_8822c(&l1_val, PCIE_BIT_L1,
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param->l1_ctrl, param_def->l1_ctrl);
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update_pcie_func_8822c(&l1_val, PCIE_BIT_WAKE,
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param->wake_ctrl, param_def->wake_ctrl);
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if (chk_stus_l1ss_8822c(adapter) == 1)
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update_pcie_func_8822c(&l1ss_val, PCIE_BIT_L1SS,
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param->l1ss_ctrl, param_def->l1ss_ctrl);
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status = update_clkdly_8822c(adapter, &clk_val,
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param->clkdly_ctrl,
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param_def->clkdly_ctrl);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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status = update_aspmdly_8822c(adapter, &aspm_val, param, param_def);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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if (param->l0s_ctrl != HALMAC_IGNORE ||
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param->l1dly_ctrl != HALMAC_L1DLY_IGNORE ||
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param->l0sdly_ctrl != HALMAC_L0SDLY_IGNORE) {
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status = dbi_w8_88xx(adapter, PCIE_ASPM_CTRL, aspm_val);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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}
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if (param->l1_ctrl != HALMAC_IGNORE ||
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param->wake_ctrl != HALMAC_IGNORE) {
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status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, l1_val);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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}
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if (param->l1ss_ctrl != HALMAC_IGNORE) {
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status = dbi_w8_88xx(adapter, PCIE_L1SS_CTRL, l1ss_val);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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}
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if (param->clkdly_ctrl != HALMAC_CLKDLY_IGNORE) {
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status = dbi_w8_88xx(adapter, PCIE_CLK_CTRL, clk_val);
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if (status != HALMAC_RET_SUCCESS)
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return status;
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}
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return HALMAC_RET_SUCCESS;
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}
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static enum halmac_ret_status
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pcie_cfgspc_read_8822c(struct halmac_adapter *adapter,
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struct halmac_pcie_cfgspc_param *param)
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{
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u8 l1_val;
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u8 aspm_val;
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u8 l1ss_val;
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u8 clk_val;
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u8 l0smask;
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u8 l1mask;
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l1_val = dbi_r8_88xx(adapter, PCIE_L1_CTRL);
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aspm_val = dbi_r8_88xx(adapter, PCIE_ASPM_CTRL);
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l1ss_val = dbi_r8_88xx(adapter, PCIE_L1SS_CTRL);
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clk_val = dbi_r8_88xx(adapter, PCIE_CLK_CTRL);
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if (l1_val == 0xFF || aspm_val == 0xFF ||
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l1ss_val == 0xFF || clk_val == 0xFF) {
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PLTFM_MSG_ERR("[ERR] (2nd)PCIE CFG reg read 0xFF!\n");
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return HALMAC_RET_FAIL;
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}
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param->l0s_ctrl = GET_PCIE_FUNC_STUS(aspm_val, PCIE_BIT_L0S);
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param->l1_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_L1);
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param->l1ss_ctrl = GET_PCIE_FUNC_STUS(l1ss_val, PCIE_BIT_L1SS);
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param->wake_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_WAKE);
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param->crq_ctrl = GET_PCIE_FUNC_STUS(l1_val, PCIE_BIT_CLK);
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switch (clk_val) {
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case PCIE_CLKDLY_HW_0:
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param->clkdly_ctrl = HALMAC_CLKDLY_0;
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break;
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case PCIE_CLKDLY_HW_30US:
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param->clkdly_ctrl = HALMAC_CLKDLY_30US;
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break;
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case PCIE_CLKDLY_HW_50US:
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param->clkdly_ctrl = HALMAC_CLKDLY_50US;
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break;
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case PCIE_CLKDLY_HW_100US:
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param->clkdly_ctrl = HALMAC_CLKDLY_100US;
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break;
|
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case PCIE_CLKDLY_HW_150US:
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param->clkdly_ctrl = HALMAC_CLKDLY_150US;
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break;
|
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case PCIE_CLKDLY_HW_200US:
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param->clkdly_ctrl = HALMAC_CLKDLY_200US;
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break;
|
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default:
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param->clkdly_ctrl = HALMAC_CLKDLY_R_ERR;
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break;
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}
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l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;
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l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;
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switch ((aspm_val & l0smask) >> SHFT_L0SDLY) {
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case PCIE_L0SDLY_HW_1US:
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param->l0sdly_ctrl = HALMAC_L0SDLY_1US;
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break;
|
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case PCIE_L0SDLY_HW_3US:
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param->l0sdly_ctrl = HALMAC_L0SDLY_3US;
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break;
|
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case PCIE_L0SDLY_HW_5US:
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param->l0sdly_ctrl = HALMAC_L0SDLY_5US;
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break;
|
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case PCIE_L0SDLY_HW_7US:
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param->l0sdly_ctrl = HALMAC_L0SDLY_7US;
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break;
|
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default:
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param->l0sdly_ctrl = HALMAC_L0SDLY_R_ERR;
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break;
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}
|
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switch ((aspm_val & l1mask) >> SHFT_L1DLY) {
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case PCIE_L1DLY_HW_16US:
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param->l1dly_ctrl = HALMAC_L1DLY_16US;
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break;
|
|
case PCIE_L1DLY_HW_32US:
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param->l1dly_ctrl = HALMAC_L1DLY_32US;
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break;
|
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case PCIE_L1DLY_HW_64US:
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param->l1dly_ctrl = HALMAC_L1DLY_64US;
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break;
|
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case PCIE_L1DLY_HW_INFI:
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param->l1dly_ctrl = HALMAC_L1DLY_INFI;
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break;
|
|
default:
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param->l1dly_ctrl = HALMAC_L1DLY_R_ERR;
|
break;
|
}
|
|
return HALMAC_RET_SUCCESS;
|
}
|
|
static void
|
update_pcie_func_8822c(u8 *val, u8 bitmask, enum halmac_func_ctrl ctrl,
|
enum halmac_func_ctrl def_ctrl)
|
{
|
if ((ctrl == HALMAC_DEFAULT &&
|
(def_ctrl == HALMAC_IGNORE || def_ctrl == HALMAC_DEFAULT)) ||
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ctrl == HALMAC_IGNORE)
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return;
|
|
if ((ctrl == HALMAC_DEFAULT && def_ctrl == HALMAC_DISABLE) ||
|
ctrl == HALMAC_DISABLE)
|
*val &= ~(bitmask);
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else
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*val |= bitmask;
|
}
|
|
static u8
|
chk_stus_l1ss_8822c(struct halmac_adapter *adapter)
|
{
|
u16 cap_val;
|
u8 stus_val;
|
u8 sup_val;
|
|
cap_val = (u16)((dbi_r8_88xx(adapter, PCIE_L1SS_CAP + 1) << 8) |
|
dbi_r8_88xx(adapter, PCIE_L1SS_CAP));
|
sup_val = dbi_r8_88xx(adapter, PCIE_L1SS_SUP);
|
stus_val = dbi_r8_88xx(adapter, PCIE_L1SS_STS);
|
|
if (cap_val == PCIE_L1SS_ID &&
|
(sup_val & PCIE_BIT_L1SSSUP) &&
|
(sup_val & PCIE_L1SS_MASK) != 0 &&
|
(stus_val & PCIE_L1SS_MASK) != 0)
|
return 1;
|
|
return 0;
|
}
|
|
static enum halmac_ret_status
|
update_clkdly_8822c(struct halmac_adapter *adapter, u8 *val,
|
enum halmac_pcie_clkdly ctrl,
|
enum halmac_pcie_clkdly def_ctrl)
|
{
|
u8 tmp;
|
|
if (ctrl == HALMAC_CLKDLY_IGNORE)
|
return HALMAC_RET_SUCCESS;
|
|
tmp = (ctrl == HALMAC_CLKDLY_DEF) ? def_ctrl : ctrl;
|
switch (tmp) {
|
case HALMAC_CLKDLY_0:
|
*val = PCIE_CLKDLY_HW_0;
|
break;
|
|
case HALMAC_CLKDLY_30US:
|
*val = PCIE_CLKDLY_HW_30US;
|
break;
|
|
case HALMAC_CLKDLY_50US:
|
*val = PCIE_CLKDLY_HW_50US;
|
break;
|
|
case HALMAC_CLKDLY_100US:
|
*val = PCIE_CLKDLY_HW_100US;
|
break;
|
|
case HALMAC_CLKDLY_150US:
|
*val = PCIE_CLKDLY_HW_150US;
|
break;
|
|
case HALMAC_CLKDLY_200US:
|
*val = PCIE_CLKDLY_HW_200US;
|
break;
|
|
default:
|
PLTFM_MSG_ERR("[ERR]CLKDLY wt val illegal!\n");
|
return HALMAC_RET_FAIL;
|
}
|
return HALMAC_RET_SUCCESS;
|
}
|
|
static enum halmac_ret_status
|
update_pcie_clk_8822c(struct halmac_adapter *adapter, u8 *val)
|
{
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
if (*val & PCIE_BIT_CLK)
|
return HALMAC_RET_SUCCESS;
|
|
if (*val & PCIE_BIT_L1) {
|
*val &= ~(PCIE_BIT_L1);
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
*val |= PCIE_BIT_CLK;
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
*val |= PCIE_BIT_L1;
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);
|
PLTFM_MSG_WARN("[WARN] L1 enable & CLKREQ disable!\n");
|
} else {
|
*val |= PCIE_BIT_CLK;
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, *val);
|
}
|
|
return status;
|
}
|
|
static enum halmac_ret_status
|
update_aspmdly_8822c(struct halmac_adapter *adapter, u8 *val,
|
struct halmac_pcie_cfgspc_param *param,
|
struct halmac_pcie_cfgspc_param *param_def)
|
{
|
u8 l1mask = PCIE_ASPMDLY_MASK << SHFT_L1DLY;
|
u8 l0smask = PCIE_ASPMDLY_MASK << SHFT_L0SDLY;
|
u8 l1updval = param->l1dly_ctrl;
|
u8 l0supdval = param->l0sdly_ctrl;
|
u8 l1defval = param_def->l1dly_ctrl;
|
u8 l0sdefval = param_def->l0sdly_ctrl;
|
u8 tmp;
|
u8 hwval;
|
|
if (l1updval != HALMAC_L1DLY_IGNORE) {
|
tmp = (l1updval == HALMAC_L1DLY_DEF) ? l1defval : l1updval;
|
switch (tmp) {
|
case HALMAC_L1DLY_16US:
|
hwval = PCIE_L1DLY_HW_16US;
|
break;
|
|
case HALMAC_L1DLY_32US:
|
hwval = PCIE_L1DLY_HW_32US;
|
break;
|
|
case HALMAC_L1DLY_64US:
|
hwval = PCIE_L1DLY_HW_64US;
|
break;
|
|
case HALMAC_L1DLY_INFI:
|
hwval = PCIE_L1DLY_HW_INFI;
|
break;
|
|
default:
|
PLTFM_MSG_ERR("[ERR]L1DLY wt val illegal!\n");
|
return HALMAC_RET_FAIL;
|
}
|
|
tmp = (hwval << SHFT_L1DLY) & l1mask;
|
*val = (*val & ~(l1mask)) | tmp;
|
}
|
|
if (l0supdval != HALMAC_L0SDLY_IGNORE) {
|
tmp = (l0supdval == HALMAC_L0SDLY_DEF) ? l0sdefval : l0supdval;
|
switch (tmp) {
|
case HALMAC_L0SDLY_1US:
|
hwval = PCIE_L0SDLY_HW_1US;
|
break;
|
|
case HALMAC_L0SDLY_3US:
|
hwval = PCIE_L0SDLY_HW_3US;
|
break;
|
|
case HALMAC_L0SDLY_5US:
|
hwval = PCIE_L0SDLY_HW_5US;
|
break;
|
|
case HALMAC_L0SDLY_7US:
|
hwval = PCIE_L0SDLY_HW_7US;
|
break;
|
|
default:
|
PLTFM_MSG_ERR("[ERR]L0SDLY wt val illegal!\n");
|
return HALMAC_RET_FAIL;
|
}
|
tmp = (hwval << SHFT_L0SDLY) & l0smask;
|
*val = (*val & ~(l0smask)) | tmp;
|
}
|
|
return HALMAC_RET_SUCCESS;
|
}
|
|
enum halmac_ret_status
|
auto_refclk_cal_8822c_pcie(struct halmac_adapter *adapter)
|
{
|
u8 bdr_ori;
|
u16 tmp_u16;
|
u16 div_set;
|
u16 mgn_tmp;
|
u16 mgn_set;
|
u16 tar;
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
u8 l1_flag = 0;
|
|
#if (INTF_INTGRA_HOSTREF_V1 <= INTF_INTGRA_MINREF_V1)
|
return status;
|
#endif
|
/* Disable L1BD */
|
bdr_ori = dbi_r8_88xx(adapter, PCIE_L1_CTRL);
|
if (bdr_ori & PCIE_BIT_L1) {
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL,
|
bdr_ori & ~(PCIE_BIT_L1));
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
l1_flag = 1;
|
}
|
|
/* Disable function */
|
tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,
|
HAL_INTF_PHY_PCIE_GEN1);
|
if (tmp_u16 & BIT(13)) {
|
status = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,
|
tmp_u16 & ~(BIT(13)),
|
HAL_INTF_PHY_PCIE_GEN1);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
}
|
if (adapter->pcie_refautok_en == 0) {
|
if (l1_flag == 1)
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, bdr_ori);
|
return status;
|
}
|
|
/* Set div */
|
tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1
|
, HAL_INTF_PHY_PCIE_GEN1);
|
status = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,
|
tmp_u16 & ~(BIT(15) | BIT(14)),
|
HAL_INTF_PHY_PCIE_GEN1);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
|
/* Obtain div and margin */
|
tar = get_target(adapter);
|
if (tar == 0xFFFF)
|
return HALMAC_RET_FAIL;
|
mgn_tmp = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar;
|
|
if (mgn_tmp >= 128) {
|
div_set = 0x0003;
|
mgn_set = 0x000F;
|
} else if (mgn_tmp >= 64) {
|
div_set = 0x0003;
|
mgn_set = mgn_tmp >> 3;
|
} else if (mgn_tmp >= 32) {
|
div_set = 0x0002;
|
mgn_set = mgn_tmp >> 2;
|
} else if (mgn_tmp >= 16) {
|
div_set = 0x0001;
|
mgn_set = mgn_tmp >> 1;
|
} else if (mgn_tmp == 0) {
|
div_set = 0x0000;
|
mgn_set = 0x0001;
|
} else {
|
div_set = 0x0000;
|
mgn_set = mgn_tmp;
|
}
|
|
/* Set div, margin, target*/
|
tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,
|
HAL_INTF_PHY_PCIE_GEN1);
|
tmp_u16 = (tmp_u16 & ~(BIT(15) | BIT(14))) | (div_set << 14);
|
status = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,
|
tmp_u16, HAL_INTF_PHY_PCIE_GEN1);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
tar = get_target(adapter);
|
if (tar == 0xFFFF)
|
return HALMAC_RET_FAIL;
|
PLTFM_MSG_TRACE("[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n",
|
tar, div_set, mgn_set);
|
status = mdio_write_88xx(adapter, RAC_SET_PPR_V1,
|
(tar & 0x0FFF) | (mgn_set << 12),
|
HAL_INTF_PHY_PCIE_GEN1);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
|
/* Enable function */
|
tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,
|
HAL_INTF_PHY_PCIE_GEN1);
|
status = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1, tmp_u16 | BIT(13),
|
HAL_INTF_PHY_PCIE_GEN1);
|
if (status != HALMAC_RET_SUCCESS)
|
return status;
|
PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
|
|
/* Set L1BD to ori */
|
if (l1_flag == 1)
|
status = dbi_w8_88xx(adapter, PCIE_L1_CTRL, bdr_ori);
|
|
return status;
|
}
|
|
static u16
|
get_target(struct halmac_adapter *adapter)
|
{
|
u16 tmp_u16;
|
u16 tar;
|
u16 count;
|
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
|
|
/* Enable counter */
|
tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,
|
HAL_INTF_PHY_PCIE_GEN1);
|
status = mdio_write_88xx(adapter, RAC_CTRL_PPR_V1,
|
tmp_u16 | BIT(12), HAL_INTF_PHY_PCIE_GEN1);
|
if (status != HALMAC_RET_SUCCESS)
|
return 0xFFFF;
|
|
/* Obtain target */
|
count = 0;
|
do {
|
PLTFM_DELAY_US(10);
|
tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1,
|
HAL_INTF_PHY_PCIE_GEN1);
|
count++;
|
if (count > 100)
|
break;
|
} while ((tmp_u16 & BIT(12)) == BIT(12));
|
if (count > 100) {
|
PLTFM_MSG_ERR("[ERR]Get target timeout.\n");
|
return 0xFFFF;
|
}
|
tar = mdio_read_88xx(adapter, RAC_CTRL_PPR_V1, HAL_INTF_PHY_PCIE_GEN1);
|
tar = tar & 0x0FFF;
|
if (tar == 0) {
|
PLTFM_MSG_ERR("[ERR]Get target failed.\n");
|
return 0xFFFF;
|
}
|
return tar;
|
}
|
|
#endif /* HALMAC_8822C_SUPPORT*/
|
