/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#ifndef _RV1126_SECURE_OTP_H_
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#define _RV1126_SECURE_OTP_H_
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#define NVM_CEB 0x00
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#define NVM_RSTB 0x04
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#define NVM_TCSRST 0x08
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#define NVM_TCEW 0x0c
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#define NVM_TRW 0x10
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#define NVM_TRS 0x14
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#define NVM_ST 0x18
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#define NVM_RADDR 0x1c
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#define NVM_RSTART 0x20
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#define NVM_RDATA 0x24
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#define NVM_TRWH 0x28
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#define NVM_TREW 0x2c
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#define NVM_READ_ST 0x30
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#define NVM_PRADDR 0x34
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#define NVM_PRLEN 0x38
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#define NVM_PRDATA 0x3c
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#define NVM_FAILTIME 0x40
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#define NVM_PRSTART 0x44
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#define NVM_PRSTATE 0x48
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#define NVM_PRSUCCESS 0x4c
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#define NVM_TAS 0x50
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#define NVM_TWWL 0x54
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#define NVM_TDLEH 0x58
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#define NVM_TDPD 0x5c
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#define NVM_TPES 0x60
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#define NVM_TCPS 0x64
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#define NVM_TPW 0x68
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#define NVM_TCPH 0x6c
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#define NVM_TPEH 0x70
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#define NVM_TPTPD 0x74
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#define NVM_TPGMAS 0x78
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#define OTPC_INT_ST 0x7c
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#define NVM_INT_EN 0x80
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#define OTP_PROG_MASK_BASE 0x0200
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#define OTP_READ_MASK_BASE 0x0300
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#define OTP_MASK_BYPASS 0x0400
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#define OTP_MASK_INT_CON 0x0404
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#define OTP_MASK_INT_STATUS 0x0408
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#define OTP_MASK_STATUS 0x040C
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#define OTP_MASK_PROG_LOCK 0x0410
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#define OTP_MASK_READ_LOCK 0x0414
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#define OTP_MASK_BYPASS_LOCK 0x0418
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#define OTP_SLICE_LOCK 0x041c
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#define OTP_SLICE 0x0420
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struct rockchip_otp_platdata {
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void __iomem *base;
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unsigned long secure_conf_base;
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};
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#endif
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