/*
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* (C) Copyright 2013
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* Texas Instruments Inc, <www.ti.com>
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_XHCI_OMAP_H_
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#define _ASM_ARCH_XHCI_OMAP_H_
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#ifdef CONFIG_DRA7XX
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#if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
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#define OMAP_XHCI_BASE 0x488d0000
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#define OMAP_OCP1_SCP_BASE 0x4A081000
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#define OMAP_OTG_WRAPPER_BASE 0x488c0000
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#elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
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#define OMAP_XHCI_BASE 0x48890000
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#define OMAP_OCP1_SCP_BASE 0x4A084c00
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#define OMAP_OTG_WRAPPER_BASE 0x48880000
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#endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
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#elif defined CONFIG_AM43XX
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#define OMAP_XHCI_BASE 0x483d0000
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#define OMAP_OCP1_SCP_BASE 0x483E8000
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#define OMAP_OTG_WRAPPER_BASE 0x483dc100
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#else
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/* Default to the OMAP5 XHCI defines */
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#define OMAP_XHCI_BASE 0x4a030000
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#define OMAP_OCP1_SCP_BASE 0x4a084c00
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#define OMAP_OTG_WRAPPER_BASE 0x4A020000
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#endif
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/* Phy register MACRO definitions */
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#define PLL_REGM_MASK 0x001FFE00
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#define PLL_REGM_SHIFT 0x9
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#define PLL_REGM_F_MASK 0x0003FFFF
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#define PLL_REGM_F_SHIFT 0x0
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#define PLL_REGN_MASK 0x000001FE
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#define PLL_REGN_SHIFT 0x1
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#define PLL_SELFREQDCO_MASK 0x0000000E
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#define PLL_SELFREQDCO_SHIFT 0x1
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#define PLL_SD_MASK 0x0003FC00
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#define PLL_SD_SHIFT 0x9
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#define SET_PLL_GO 0x1
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#define PLL_TICOPWDN 0x10000
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#define PLL_LOCK 0x2
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#define PLL_IDLE 0x1
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#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
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#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
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#define USB3_PHY_PARTIAL_RX_POWERON (1 << 6)
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#define USB3_PHY_RX_POWERON (1 << 14)
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#define USB3_PHY_TX_POWERON (1 << 15)
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#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
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#define USB3_PWRCTL_CLK_CMD_SHIFT 14
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#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
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/* USBOTGSS_WRAPPER definitions */
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#define USBOTGSS_WRAPRESET (1 << 17)
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#define USBOTGSS_DMADISABLE (1 << 16)
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#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
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#define USBOTGSS_STANDBYMODE_SMRT (1 << 5)
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#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
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#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
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#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
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#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
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/* USBOTGSS_IRQENABLE_SET_0 bit */
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#define USBOTGSS_COREIRQ_EN (1 << 0)
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/* USBOTGSS_IRQENABLE_SET_1 bits */
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN (1 << 0)
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN (1 << 3)
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN (1 << 4)
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN (1 << 5)
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN (1 << 8)
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN (1 << 11)
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN (1 << 12)
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN (1 << 13)
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#define USBOTGSS_IRQ_SET_1_OEVT_EN (1 << 16)
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#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN (1 << 17)
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/*
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* USBOTGSS_WRAPPER registers
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*/
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struct omap_dwc_wrapper {
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u32 revision;
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u32 reserve_1[3];
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u32 sysconfig; /* offset of 0x10 */
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u32 reserve_2[3];
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u16 reserve_3;
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u32 irqstatus_raw_0; /* offset of 0x24 */
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u32 irqstatus_0;
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u32 irqenable_set_0;
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u32 irqenable_clr_0;
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u32 irqstatus_raw_1; /* offset of 0x34 */
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u32 irqstatus_1;
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u32 irqenable_set_1;
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u32 irqenable_clr_1;
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u32 reserve_4[15];
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u32 utmi_otg_ctrl; /* offset of 0x80 */
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u32 utmi_otg_status;
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u32 reserve_5[30];
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u32 mram_offset; /* offset of 0x100 */
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u32 fladj;
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u32 dbg_config;
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u32 dbg_data;
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u32 dev_ebc_en;
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};
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/* XHCI PHY register structure */
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struct omap_usb3_phy {
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u32 reserve1;
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u32 pll_status;
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u32 pll_go;
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u32 pll_config_1;
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u32 pll_config_2;
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u32 pll_config_3;
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u32 pll_ssc_config_1;
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u32 pll_ssc_config_2;
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u32 pll_config_4;
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};
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struct omap_xhci {
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struct omap_dwc_wrapper *otg_wrapper;
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struct omap_usb3_phy *usb3_phy;
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struct xhci_hccr *hcd;
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struct dwc3 *dwc3_reg;
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};
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/* USB PHY functions */
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void omap_enable_phy(struct omap_xhci *omap);
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void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
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void usb_phy_power(int on);
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#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
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