/* include/linux/usb/dwc3.h
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*
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* Copyright (c) 2012 Samsung Electronics Co. Ltd
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*
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* Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DWC3_H_
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#define __DWC3_H_
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/* Global constants */
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#define DWC3_ENDPOINTS_NUM 32
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#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
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#define DWC3_EVENT_TYPE_MASK 0xfe
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#define DWC3_EVENT_TYPE_DEV 0
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#define DWC3_EVENT_TYPE_CARKIT 3
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#define DWC3_EVENT_TYPE_I2C 4
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#define DWC3_DEVICE_EVENT_DISCONNECT 0
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#define DWC3_DEVICE_EVENT_RESET 1
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#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
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#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
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#define DWC3_DEVICE_EVENT_WAKEUP 4
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#define DWC3_DEVICE_EVENT_EOPF 6
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#define DWC3_DEVICE_EVENT_SOF 7
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#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
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#define DWC3_DEVICE_EVENT_CMD_CMPL 10
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#define DWC3_DEVICE_EVENT_OVERFLOW 11
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#define DWC3_GEVNTCOUNT_MASK 0xfffc
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#define DWC3_GSNPSID_MASK 0xffff0000
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#define DWC3_GSNPSID_SHIFT 16
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#define DWC3_GSNPSREV_MASK 0xffff
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#define DWC3_REVISION_MASK 0xffff
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#define DWC3_REG_OFFSET 0xC100
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struct g_event_buffer {
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u32 g_evntadrlo;
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u32 g_evntadrhi;
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u32 g_evntsiz;
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u32 g_evntcount;
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};
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struct d_physical_endpoint {
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u32 d_depcmdpar2;
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u32 d_depcmdpar1;
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u32 d_depcmdpar0;
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u32 d_depcmd;
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};
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struct dwc3 { /* offset: 0xC100 */
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u32 g_sbuscfg0;
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u32 g_sbuscfg1;
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u32 g_txthrcfg;
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u32 g_rxthrcfg;
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u32 g_ctl;
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u32 reserved1;
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u32 g_sts;
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u32 reserved2;
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u32 g_snpsid;
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u32 g_gpio;
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u32 g_uid;
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u32 g_uctl;
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u64 g_buserraddr;
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u64 g_prtbimap;
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u32 g_hwparams0;
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u32 g_hwparams1;
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u32 g_hwparams2;
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u32 g_hwparams3;
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u32 g_hwparams4;
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u32 g_hwparams5;
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u32 g_hwparams6;
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u32 g_hwparams7;
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u32 g_dbgfifospace;
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u32 g_dbgltssm;
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u32 g_dbglnmcc;
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u32 g_dbgbmu;
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u32 g_dbglspmux;
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u32 g_dbglsp;
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u32 g_dbgepinfo0;
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u32 g_dbgepinfo1;
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u64 g_prtbimap_hs;
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u64 g_prtbimap_fs;
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u32 reserved3[28];
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u32 g_usb2phycfg[16];
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u32 g_usb2i2cctl[16];
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u32 g_usb2phyacc[16];
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u32 g_usb3pipectl[16];
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u32 g_txfifosiz[32];
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u32 g_rxfifosiz[32];
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struct g_event_buffer g_evnt_buf[32];
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u32 g_hwparams8;
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u32 reserved4[11];
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u32 g_fladj;
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u32 reserved5[51];
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u32 d_cfg;
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u32 d_ctl;
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u32 d_evten;
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u32 d_sts;
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u32 d_gcmdpar;
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u32 d_gcmd;
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u32 reserved6[2];
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u32 d_alepena;
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u32 reserved7[55];
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struct d_physical_endpoint d_phy_ep_cmd[32];
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u32 reserved8[128];
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u32 o_cfg;
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u32 o_ctl;
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u32 o_evt;
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u32 o_evten;
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u32 o_sts;
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u32 reserved9[3];
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u32 adp_cfg;
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u32 adp_ctl;
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u32 adp_evt;
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u32 adp_evten;
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u32 bc_cfg;
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u32 reserved10;
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u32 bc_evt;
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u32 bc_evten;
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};
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/* Global Configuration Register */
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#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
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#define DWC3_GCTL_U2RSTECN (1 << 16)
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#define DWC3_GCTL_RAMCLKSEL(x) \
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(((x) & DWC3_GCTL_CLK_MASK) << 6)
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#define DWC3_GCTL_CLK_BUS (0)
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#define DWC3_GCTL_CLK_PIPE (1)
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#define DWC3_GCTL_CLK_PIPEHALF (2)
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#define DWC3_GCTL_CLK_MASK (3)
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#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
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#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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#define DWC3_GCTL_PRTCAP_HOST 1
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#define DWC3_GCTL_PRTCAP_DEVICE 2
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* Global HWPARAMS1 Register */
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#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
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#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
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#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
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#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
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/* Global USB2 PHY Configuration Mask */
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
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/* Global USB2 PHY Configuration Offset */
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
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DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
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DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB3PIPECTL_DISRXDETP3 (1 << 28)
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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/* Global TX Fifo Size Register */
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#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
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#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
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/* Device Control Register */
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#define DWC3_DCTL_RUN_STOP (1 << 31)
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#define DWC3_DCTL_CSFTRST (1 << 30)
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#define DWC3_DCTL_LSFTRST (1 << 29)
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/* Global Frame Length Adjustment Register */
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#define GFLADJ_30MHZ_REG_SEL (1 << 7)
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#define GFLADJ_30MHZ(n) ((n) & 0x3f)
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#define GFLADJ_30MHZ_DEFAULT 0x20
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#ifdef CONFIG_USB_XHCI_DWC3
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void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
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void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
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int dwc3_core_init(struct dwc3 *dwc3_reg);
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void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
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#endif
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#endif /* __DWC3_H_ */
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