/*
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* (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ROCKCHIP_MIPI_DSI_H__
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#define __ROCKCHIP_MIPI_DSI_H__
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#define BIT(nr) (1UL << (nr))
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/* request ACK from peripheral */
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#define MIPI_DSI_MSG_REQ_ACK BIT(0)
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/* use Low Power Mode to transmit message */
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#define MIPI_DSI_MSG_USE_LPM BIT(1)
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/* DSI mode flags */
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/* video mode */
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#define MIPI_DSI_MODE_VIDEO BIT(0)
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/* video burst mode */
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#define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
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/* video pulse mode */
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#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
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/* enable auto vertical count mode */
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#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3)
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/* enable hsync-end packets in vsync-pulse and v-porch area */
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#define MIPI_DSI_MODE_VIDEO_HSE BIT(4)
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/* disable hfront-porch area */
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#define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
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/* disable hback-porch area */
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#define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
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/* disable hsync-active area */
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#define MIPI_DSI_MODE_VIDEO_HSA BIT(7)
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/* flush display FIFO on vsync pulse */
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#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
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/* disable EoT packets in HS mode */
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#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
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/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
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#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
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/* transmit data in low power */
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#define MIPI_DSI_MODE_LPM BIT(11)
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#define MIPI_DSI_DCS_POWER_MODE_DISPLAY BIT(2)
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#define MIPI_DSI_DCS_POWER_MODE_NORMAL BIT(3)
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#define MIPI_DSI_DCS_POWER_MODE_SLEEP BIT(4)
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#define MIPI_DSI_DCS_POWER_MODE_PARTIAL BIT(5)
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#define MIPI_DSI_DCS_POWER_MODE_IDLE BIT(6)
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#define MIPI_DSI_FMT_RGB888 0
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#define MIPI_DSI_FMT_RGB666 1
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#define MIPI_DSI_FMT_RGB666_PACKED 2
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#define MIPI_DSI_FMT_RGB565 3
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#endif /* __ROCKCHIP_MIPI_DSI__ */
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