/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
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#define __DT_BINDINGS_CLOCK_IMX7ULP_H
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#define IMX7ULP_CLK_DUMMY 0
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#define IMX7ULP_CLK_CKIL 1
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#define IMX7ULP_CLK_OSC 2
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#define IMX7ULP_CLK_FIRC 3
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/* SCG1 */
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#define IMX7ULP_CLK_SPLL_PRE_SEL 4
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#define IMX7ULP_CLK_SPLL_PRE_DIV 5
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#define IMX7ULP_CLK_SPLL 6
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#define IMX7ULP_CLK_SPLL_POST_DIV1 7
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#define IMX7ULP_CLK_SPLL_POST_DIV2 8
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#define IMX7ULP_CLK_SPLL_PFD0 9
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#define IMX7ULP_CLK_SPLL_PFD1 10
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#define IMX7ULP_CLK_SPLL_PFD2 11
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#define IMX7ULP_CLK_SPLL_PFD3 12
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#define IMX7ULP_CLK_SPLL_PFD_SEL 13
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#define IMX7ULP_CLK_SPLL_SEL 14
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#define IMX7ULP_CLK_APLL_PRE_SEL 15
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#define IMX7ULP_CLK_APLL_PRE_DIV 16
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#define IMX7ULP_CLK_APLL 17
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#define IMX7ULP_CLK_APLL_POST_DIV1 18
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#define IMX7ULP_CLK_APLL_POST_DIV2 19
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#define IMX7ULP_CLK_APLL_PFD0 20
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#define IMX7ULP_CLK_APLL_PFD1 21
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#define IMX7ULP_CLK_APLL_PFD2 22
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#define IMX7ULP_CLK_APLL_PFD3 23
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#define IMX7ULP_CLK_APLL_PFD_SEL 24
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#define IMX7ULP_CLK_APLL_SEL 25
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#define IMX7ULP_CLK_UPLL 26
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#define IMX7ULP_CLK_SYS_SEL 27
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#define IMX7ULP_CLK_CORE_DIV 28
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#define IMX7ULP_CLK_BUS_DIV 29
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#define IMX7ULP_CLK_PLAT_DIV 30
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#define IMX7ULP_CLK_DDR_SEL 31
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#define IMX7ULP_CLK_DDR_DIV 32
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#define IMX7ULP_CLK_NIC_SEL 33
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#define IMX7ULP_CLK_NIC0_DIV 34
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#define IMX7ULP_CLK_GPU_DIV 35
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#define IMX7ULP_CLK_NIC1_DIV 36
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#define IMX7ULP_CLK_NIC1_BUS_DIV 37
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#define IMX7ULP_CLK_NIC1_EXT_DIV 38
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/* PCG2 */
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#define IMX7ULP_CLK_DMA1 39
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#define IMX7ULP_CLK_RGPIO2P1 40
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#define IMX7ULP_CLK_FLEXBUS 41
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#define IMX7ULP_CLK_SEMA42_1 42
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#define IMX7ULP_CLK_DMA_MUX1 43
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#define IMX7ULP_CLK_SNVS 44
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#define IMX7ULP_CLK_CAAM 45
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#define IMX7ULP_CLK_LPTPM4 46
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#define IMX7ULP_CLK_LPTPM5 47
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#define IMX7ULP_CLK_LPIT1 48
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#define IMX7ULP_CLK_LPSPI2 49
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#define IMX7ULP_CLK_LPSPI3 50
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#define IMX7ULP_CLK_LPI2C4 51
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#define IMX7ULP_CLK_LPI2C5 52
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#define IMX7ULP_CLK_LPUART4 53
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#define IMX7ULP_CLK_LPUART5 54
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#define IMX7ULP_CLK_FLEXIO1 55
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#define IMX7ULP_CLK_USB0 56
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#define IMX7ULP_CLK_USB1 57
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#define IMX7ULP_CLK_USB_PHY 58
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#define IMX7ULP_CLK_USB_PL301 59
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#define IMX7ULP_CLK_USDHC0 60
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#define IMX7ULP_CLK_USDHC1 61
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#define IMX7ULP_CLK_WDG1 62
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#define IMX7ULP_CLK_WDG2 63
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/* PCG3 */
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#define IMX7ULP_CLK_LPTPM6 64
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#define IMX7ULP_CLK_LPTPM7 65
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#define IMX7ULP_CLK_LPI2C6 66
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#define IMX7ULP_CLK_LPI2C7 67
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#define IMX7ULP_CLK_LPUART6 68
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#define IMX7ULP_CLK_LPUART7 69
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#define IMX7ULP_CLK_VIU 70
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#define IMX7ULP_CLK_DSI 71
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#define IMX7ULP_CLK_LCDIF 72
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#define IMX7ULP_CLK_MMDC 73
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#define IMX7ULP_CLK_PCTLC 74
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#define IMX7ULP_CLK_PCTLD 75
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#define IMX7ULP_CLK_PCTLE 76
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#define IMX7ULP_CLK_PCTLF 77
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#define IMX7ULP_CLK_GPU3D 78
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#define IMX7ULP_CLK_GPU2D 79
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#define IMX7ULP_CLK_MIPI_PLL 80
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#define IMX7ULP_CLK_SIRC 81
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#define IMX7ULP_CLK_SCG1_CLKOUT 82
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#define IMX7ULP_CLK_END 83
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/*cm4 clocks*/
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#define IMX7ULP_CM4_CLK_DUMMY 0
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#define IMX7ULP_CM4_CLK_CKIL 1
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#define IMX7ULP_CM4_CLK_OSC 2
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#define IMX7ULP_CM4_CLK_FIRC 3
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#define IMX7ULP_CM4_CLK_SIRC 4
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/* SCG0 */
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#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5
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#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6
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#define IMX7ULP_CM4_CLK_SPLL 7
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#define IMX7ULP_CM4_CLK_SPLL_VCO 8
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#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9
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#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10
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#define IMX7ULP_CM4_CLK_SPLL_PFD0 11
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#define IMX7ULP_CM4_CLK_SPLL_PFD1 12
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#define IMX7ULP_CM4_CLK_SPLL_PFD2 13
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#define IMX7ULP_CM4_CLK_SPLL_PFD3 14
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#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15
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#define IMX7ULP_CM4_CLK_SPLL_PFD 16
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#define IMX7ULP_CM4_CLK_SPLL_SEL 17
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#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18
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#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19
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#define IMX7ULP_CM4_CLK_APLL 20
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#define IMX7ULP_CM4_CLK_APLL_VCO 21
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#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22
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#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23
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#define IMX7ULP_CM4_CLK_APLL_PFD0 24
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#define IMX7ULP_CM4_CLK_APLL_PFD1 25
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#define IMX7ULP_CM4_CLK_APLL_PFD2 26
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#define IMX7ULP_CM4_CLK_APLL_PFD3 27
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#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28
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#define IMX7ULP_CM4_CLK_APLL_PFD 29
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#define IMX7ULP_CM4_CLK_APLL_SEL 30
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#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31
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#define IMX7ULP_CM4_CLK_SYS_SEL 32
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#define IMX7ULP_CM4_CLK_CORE_DIV 33
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#define IMX7ULP_CM4_CLK_BUS_DIV 34
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#define IMX7ULP_CM4_CLK_PLAT_DIV 35
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#define IMX7ULP_CM4_CLK_SLOW_DIV 36
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#define IMX7ULP_CM4_CLK_SAI0_SEL 37
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#define IMX7ULP_CM4_CLK_SAI0_DIV 38
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#define IMX7ULP_CM4_CLK_SAI0_ROOT 39
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#define IMX7ULP_CM4_CLK_SAI0_IPG 40
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#define IMX7ULP_CM4_CLK_SAI1_SEL 41
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#define IMX7ULP_CM4_CLK_SAI1_DIV 42
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#define IMX7ULP_CM4_CLK_SAI1_ROOT 43
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#define IMX7ULP_CM4_CLK_SAI1_IPG 44
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#define IMX7ULP_CLK_SCG0_CLKOUT 45
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#define IMX7ULP_CM4_CLK_END 46
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#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
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