/*
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* Copyright 2010 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* xpedite550x board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_XPEDITE550X 1
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#define CONFIG_SYS_BOARD_NAME "XPedite5500"
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#define CONFIG_SYS_FORM_PMC_XMC 1
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#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
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#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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#endif
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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/*
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* Multicore config
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*/
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#define CONFIG_MP
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#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
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#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
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/*
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* DDR config
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*/
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_DDR_SPD
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define SPD_EEPROM_ADDRESS 0x54
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#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_VERY_BIG_RAM
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#define CONFIG_SYS_CCSRBAR 0xef000000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/*
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* Diagnostics
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*/
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x10000000
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#define CONFIG_SYS_MEMTEST_END 0x20000000
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_I2C)
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#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
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CONFIG_SYS_I2C_LM75_ADDR, \
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CONFIG_SYS_I2C_LM90_ADDR, \
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CONFIG_SYS_I2C_PCA953X_ADDR0, \
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CONFIG_SYS_I2C_PCA953X_ADDR2, \
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CONFIG_SYS_I2C_PCA953X_ADDR3, \
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CONFIG_SYS_I2C_RTC_ADDR}
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/*
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* Memory map
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* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
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* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
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* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
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* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
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* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
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* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
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* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
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*/
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#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
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/*
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* NAND flash configuration
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*/
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#define CONFIG_SYS_NAND_BASE 0xef800000
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#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
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CONFIG_SYS_NAND_BASE2}
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#define CONFIG_SYS_MAX_NAND_DEVICE 2
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#define CONFIG_NAND_FSL_ELBC
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/*
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* NOR flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE 0xf8000000
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#define CONFIG_SYS_FLASH_BASE2 0xf0000000
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
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{0xf7f40000, 0xc0000} }
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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/*
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* Chip select configuration
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*/
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/* NOR Flash 0 on CS0 */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
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BR_PS_16 | \
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BR_V)
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#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
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OR_GPCM_CSNT | \
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OR_GPCM_XACS | \
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OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_8 | \
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OR_GPCM_TRLX | \
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OR_GPCM_EHTR | \
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OR_GPCM_EAD)
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/* NOR Flash 1 on CS1 */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
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BR_PS_16 | \
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BR_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
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/* NAND flash on CS2 */
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
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(2<<BR_DECC_SHIFT) | \
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BR_PS_8 | \
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BR_MS_FCM | \
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BR_V)
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/* NAND flash on CS2 */
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#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
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OR_FCM_PGS | \
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OR_FCM_CSCT | \
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OR_FCM_CST | \
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OR_FCM_CHT | \
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OR_FCM_SCY_1 | \
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OR_FCM_TRLX | \
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OR_FCM_EHTR)
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/* NAND flash on CS3 */
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
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(2<<BR_DECC_SHIFT) | \
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BR_PS_8 | \
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BR_MS_FCM | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
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/*
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* Use L1 as initial stack
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_FDT_FIXUP_PCI_IRQ 1
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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/* I2C DS7505 temperature sensor */
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#define CONFIG_SYS_I2C_LM75_ADDR 0x48
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/* I2C ADT7461 temperature sensor */
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#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
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/* I2C EEPROM - AT24C128B */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
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/* I2C RTC */
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#define CONFIG_RTC_M41T11 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_M41T11_BASE_YEAR 2000
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/* GPIO */
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#define CONFIG_PCA953X
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#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
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#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
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#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
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#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
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#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
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/*
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* GPIO pin definitions, PU = pulled high, PD = pulled low
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*/
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/* PCA9557 @ 0x18*/
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#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
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#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
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#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
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#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
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#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
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#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
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/* PCA9557 @ 0x1e*/
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#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
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#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
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#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
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#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
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#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
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#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
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#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
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/* PCA9557 @ 0x1f */
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#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
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#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1 - PEX8112 or XMC, depending on build option */
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
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/*
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* Networking options
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*/
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_TBI
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_ETHPRIME "eTSEC2"
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/*
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* In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
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* 1000mbps SGMII link
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*/
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#define CONFIG_TSEC_TBICR_SETTINGS ( \
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TBICR_PHY_RESET \
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| TBICR_FULL_DUPLEX \
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| TBICR_SPEED1_SET \
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)
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_PHY_ADDR 2
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#define TSEC2_PHYIDX 0
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_PHY_ADDR 3
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#define TSEC3_PHYIDX 0
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#define CONFIG_HAS_ETH2
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/*
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* USB
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*/
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
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#define CONFIG_ENV_SIZE 0x8000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
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/*
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* Flash memory map:
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* fff80000 - ffffffff Pri U-Boot (512 KB)
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* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
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* fff00000 - fff3ffff Pri FDT (256KB)
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* fef00000 - ffefffff Pri OS image (16MB)
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* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
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*
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* f7f80000 - f7ffffff Sec U-Boot (512 KB)
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* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
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* f7f00000 - f7f3ffff Sec FDT (256KB)
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* f6f00000 - f7efffff Sec OS image (16MB)
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* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
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*/
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#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
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#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
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#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
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#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
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#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
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#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
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#define CONFIG_PROG_UBOOT1 \
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"$download_cmd $loadaddr $ubootfile; " \
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"if test $? -eq 0; then " \
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"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
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"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
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"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
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"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
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"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
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"if test $? -ne 0; then " \
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"echo PROGRAM FAILED; " \
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"else; " \
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"echo PROGRAM SUCCEEDED; " \
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"fi; " \
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"else; " \
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"echo DOWNLOAD FAILED; " \
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"fi;"
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#define CONFIG_PROG_UBOOT2 \
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"$download_cmd $loadaddr $ubootfile; " \
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"if test $? -eq 0; then " \
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"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
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"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
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"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
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"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
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"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
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"if test $? -ne 0; then " \
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"echo PROGRAM FAILED; " \
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"else; " \
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"echo PROGRAM SUCCEEDED; " \
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"fi; " \
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"else; " \
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"echo DOWNLOAD FAILED; " \
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"fi;"
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#define CONFIG_BOOT_OS_NET \
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"$download_cmd $osaddr $osfile; " \
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"if test $? -eq 0; then " \
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"if test -n $fdtaddr; then " \
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"$download_cmd $fdtaddr $fdtfile; " \
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"if test $? -eq 0; then " \
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"bootm $osaddr - $fdtaddr; " \
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"else; " \
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"echo FDT DOWNLOAD FAILED; " \
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"fi; " \
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"else; " \
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"bootm $osaddr; " \
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"fi; " \
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"else; " \
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"echo OS DOWNLOAD FAILED; " \
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"fi;"
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#define CONFIG_PROG_OS1 \
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"$download_cmd $osaddr $osfile; " \
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"if test $? -eq 0; then " \
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"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
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"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
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"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
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"if test $? -ne 0; then " \
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"echo OS PROGRAM FAILED; " \
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"else; " \
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"echo OS PROGRAM SUCCEEDED; " \
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"fi; " \
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"else; " \
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"echo OS DOWNLOAD FAILED; " \
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"fi;"
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#define CONFIG_PROG_OS2 \
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"$download_cmd $osaddr $osfile; " \
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"if test $? -eq 0; then " \
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"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
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"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
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"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
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"if test $? -ne 0; then " \
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"echo OS PROGRAM FAILED; " \
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"else; " \
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"echo OS PROGRAM SUCCEEDED; " \
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"fi; " \
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"else; " \
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"echo OS DOWNLOAD FAILED; " \
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"fi;"
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|
#define CONFIG_PROG_FDT1 \
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"$download_cmd $fdtaddr $fdtfile; " \
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"if test $? -eq 0; then " \
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"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
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"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
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"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
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"if test $? -ne 0; then " \
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"echo FDT PROGRAM FAILED; " \
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"else; " \
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"echo FDT PROGRAM SUCCEEDED; " \
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"fi; " \
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"else; " \
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"echo FDT DOWNLOAD FAILED; " \
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"fi;"
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|
#define CONFIG_PROG_FDT2 \
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"$download_cmd $fdtaddr $fdtfile; " \
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"if test $? -eq 0; then " \
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"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
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"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
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"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
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"if test $? -ne 0; then " \
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"echo FDT PROGRAM FAILED; " \
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"else; " \
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"echo FDT PROGRAM SUCCEEDED; " \
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"fi; " \
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"else; " \
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"echo FDT DOWNLOAD FAILED; " \
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"fi;"
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
"autoload=yes\0" \
|
"download_cmd=tftp\0" \
|
"console_args=console=ttyS0,115200\0" \
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"root_args=root=/dev/nfs rw\0" \
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"misc_args=ip=on\0" \
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"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
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"bootfile=/home/user/file\0" \
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"osfile=/home/user/board.uImage\0" \
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"fdtfile=/home/user/board.dtb\0" \
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"ubootfile=/home/user/u-boot.bin\0" \
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"fdtaddr=0x1e00000\0" \
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"osaddr=0x1000000\0" \
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"loadaddr=0x1000000\0" \
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"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
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"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
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"prog_os1="CONFIG_PROG_OS1"\0" \
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"prog_os2="CONFIG_PROG_OS2"\0" \
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"prog_fdt1="CONFIG_PROG_FDT1"\0" \
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"prog_fdt2="CONFIG_PROG_FDT2"\0" \
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"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
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"bootcmd_flash1=run set_bootargs; " \
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"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
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"bootcmd_flash2=run set_bootargs; " \
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"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
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"bootcmd=run bootcmd_flash1\0"
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#endif /* __CONFIG_H */
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