/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the WB45N CPU Module.
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*/
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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#include <asm/hardware.h>
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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#define CONFIG_AT91_GPIO
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* NAND flash */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB_SEARCH_PHY
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#define CONFIG_ETHADDR C0:EE:40:00:00:00
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#define CONFIG_ENV_OVERWRITE 1
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/* System */
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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#ifdef CONFIG_SYS_USE_NANDFLASH
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/* bootstrap + u-boot + env + linux in nandflash */
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#define CONFIG_ENV_OFFSET 0xa0000
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#define CONFIG_ENV_OFFSET_REDUND 0xc0000
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#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */
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#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \
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"run _mtd; bootm"
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#define MTDIDS_DEFAULT "nand0=atmel_nand"
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#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \
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"128K(at91bs)," \
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"512K(u-boot)," \
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"128K(u-boot-env)," \
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"128K(redund-env)," \
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"2560K(kernel-a)," \
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"2560K(kernel-b)," \
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"38912K(rootfs-a)," \
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"38912K(rootfs-b)," \
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"46208K(user)," \
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"512K(logs)"
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#else
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#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
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#endif
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#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \
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"rw noinitrd mem=64M " \
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"rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \
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"autoload=no\0" \
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"autostart=no\0" \
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"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
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"\0"
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
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/* SPL */
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x6000
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#define CONFIG_SPL_STACK 0x308000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#define CONFIG_SYS_MASTER_CLOCK 132096000
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#define CONFIG_SYS_AT91_PLLA 0x20c73f03
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#endif /* __CONFIG_H__ */
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