/*
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* ti816x_evm.h
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_TI816X_EVM_H
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#define __CONFIG_TI816X_EVM_H
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#include <configs/ti_armv7_omap.h>
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#include <asm/arch/omap.h>
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_LINUX_BOOT_ENV \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan;" \
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"fatload mmc 0 ${loadaddr} uImage;" \
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"bootm ${loadaddr}" \
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/* Clock Defines */
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#define V_OSCK 24000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_CMD_ASKENV
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#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/**
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* Platform/Board specific defs
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*/
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#define CONFIG_SYS_CLK_FREQ 27000000
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#define CONFIG_SYS_TIMERBASE 0x4802E000
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK (48000000)
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#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
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/* allow overwriting serial config and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SERIAL1
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#define CONFIG_SERIAL2
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#define CONFIG_SERIAL3
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#define CONFIG_CONS_INDEX 1
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/*
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* GPMC NAND block. We support 1 device and the physical address to
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* access CS0 at is 0x8000000.
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*/
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#define CONFIG_SYS_NAND_BASE 0x8000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* NAND: SPL related configs */
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/* NAND: device related configs */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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/* NAND: driver related configs */
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, \
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26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, \
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42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, }
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define MTDIDS_DEFAULT "nand0=nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
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"128k(NAND.SPL)," \
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"128k(NAND.SPL.backup1)," \
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"128k(NAND.SPL.backup2)," \
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"128k(NAND.SPL.backup3)," \
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"256k(NAND.u-boot-spl-os)," \
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"1m(NAND.u-boot)," \
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"128k(NAND.u-boot-env)," \
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"128k(NAND.u-boot-env.backup1)," \
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"8m(NAND.kernel)," \
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"-(NAND.file-system)"
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
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#define CONFIG_ENV_OFFSET 0x001c0000
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#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
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#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x40400000
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SYS_TEXT_BASE 0x80800000
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_NET_RETRY_COUNT 10
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/* Since SPL did pll and ddr initialization for us,
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* we don't need to do it twice.
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*/
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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/*
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* Disable MMC DM for SPL build and can be re-enabled after adding
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* DM support in SPL
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*/
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#ifdef CONFIG_SPL_BUILD
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#undef CONFIG_DM_MMC
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#undef CONFIG_TIMER
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#endif
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#endif
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