/*
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* (C) Copyright 2014
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* Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_STV0991_H
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#define __CONFIG_STV0991_H
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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#define CONFIG_SYS_CORTEX_R4
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/* ram memory-related information */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x00000000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define PHYS_SDRAM_1_SIZE 0x00198000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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#define CONFIG_ENV_OFFSET 0x30000
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#define CONFIG_ENV_ADDR \
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(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
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/* serial port (PL011) configuration */
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#define CONFIG_PL01X_SERIAL
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/* user interface */
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#define CONFIG_SYS_CBSIZE 1024
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/* MISC */
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#define CONFIG_SYS_LOAD_ADDR 0x00000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
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#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/* U-Boot Load Address */
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#define CONFIG_SYS_TEXT_BASE 0x00010000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* GMAC related configs */
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#define CONFIG_MII
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#define CONFIG_DW_ALTDESCRIPTOR
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/* Command support defines */
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#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
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#define CONFIG_SYS_MEMTEST_START 0x0000
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#define CONFIG_SYS_MEMTEST_END 1024*1024
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/* Misc configuration */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_BOOTCOMMAND "go 0x40040000"
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/*
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+ * QSPI support
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+ */
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#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
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#define CONFIG_CQSPI_DECODER 0
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#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
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#endif
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#endif /* __CONFIG_H */
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