/*
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* Sysam stmark2 board configuration
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __STMARK2_CONFIG_H
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#define __STMARK2_CONFIG_H
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#define CONFIG_STMARK2
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#define CONFIG_HOSTNAME stmark2
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT 0
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#define LDS_BOARD_TEXT \
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board/sysam/stmark2/sbf_dram_init.o (.text*)
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTARGS \
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"console=ttyS0,115200 root=/dev/ram0 rw " \
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"rootfstype=ramfs " \
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"rdinit=/bin/init " \
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"devtmpfs.mount=1"
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#define CONFIG_BOOTCOMMAND \
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"sf probe 0:1 50000000; " \
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"sf read ${loadaddr} 0x100000 ${kern_size}; " \
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"bootm ${loadaddr}"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kern_size=0x700000\0" \
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"loadaddr=0x40001000\0" \
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"-(rootfs)\0" \
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"update_uboot=loady ${loadaddr}; " \
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"sf probe 0:1 50000000; " \
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"sf erase 0 0x80000; " \
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"sf write ${loadaddr} 0 ${filesize}\0" \
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"update_kernel=loady ${loadaddr}; " \
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"setenv kern_size ${filesize}; saveenv; " \
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"sf probe 0:1 50000000; " \
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"sf erase 0x100000 0x700000; " \
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"sf write ${loadaddr} 0x100000 ${filesize}\0" \
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"update_rootfs=loady ${loadaddr}; " \
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"sf probe 0:1 50000000; " \
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"sf erase 0x00800000 0x100000; " \
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"sf write ${loadaddr} 0x00800000 ${filesize}\0" \
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""
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/* Realtime clock */
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#undef CONFIG_MCFRTC
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#define CONFIG_RTC_MCFRRTC
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#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
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/* spi not partitions */
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#define MTDIDS_DEFAULT "nor0=spi-flash.0"
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#define MTDPARTS_DEFAULT \
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"mtdparts=spi-flash.0:" \
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"1m(u-boot)," \
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"7m(kernel)," \
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"-(rootfs)"
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/* Timer */
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* DSPI and Serial Flash */
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#define CONFIG_CF_DSPI
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 1
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#define CONFIG_SYS_SBFHDR_SIZE 0x7
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#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
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DSPI_CTAR_PCSSCK_1CLK | \
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DSPI_CTAR_PASC(0) | \
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DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(0) | \
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DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(1) | \
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DSPI_CTAR_BR(6))
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#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
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#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
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/* Input, PCI, Flexbus, and VCO */
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#define CONFIG_EXTRA_CLOCK
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#define CONFIG_PRAM 2048 /* 2048 KB */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
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#define CONFIG_SYS_MBAR 0xFC000000
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/*
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* Definitions for initial stack pointer and data area (in internal SRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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/* End of used area in internal SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#define CONFIG_SYS_INIT_RAM_CTRL 0x221
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE) - 32)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
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#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
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#define CONFIG_SYS_DRAM_TEST
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#if defined(CONFIG_CF_SBF)
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#define CONFIG_SERIAL_BOOT
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#endif
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#if defined(CONFIG_SERIAL_BOOT)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
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#else
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#endif
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#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
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/* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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/* Reserve 256 kB for malloc() */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
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(CONFIG_SYS_SDRAM_SIZE << 20))
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#if defined(CONFIG_CF_SBF)
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SPI_CS 1
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#endif
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#undef CONFIG_ENV_OVERWRITE
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
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#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
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#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
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CF_CACR_ICINVA | CF_CACR_EUSP)
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#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
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CF_CACR_DEC | CF_CACR_DDCM_P | \
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CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
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#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 12)
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#endif /* __STMARK2_CONFIG_H */
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