/*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_STM32F4DISCOVERY
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_FLASH_BASE 0x08000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
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#define CONFIG_SYS_TEXT_BASE 0x08000000
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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/*
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* Configuration of the external SDRAM memory
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_RAM_SIZE (8 << 20)
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#define CONFIG_SYS_RAM_CS 1
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#define CONFIG_SYS_RAM_FREQ_DIV 2
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#define CONFIG_SYS_RAM_BASE 0xD0000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
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#define CONFIG_SYS_LOAD_ADDR 0xD0400000
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#define CONFIG_LOADADDR 0xD0400000
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#define CONFIG_SYS_MAX_FLASH_SECT 12
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_ENV_OFFSET (256 << 10)
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#define CONFIG_ENV_SECT_SIZE (128 << 10)
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#define CONFIG_ENV_SIZE (8 << 10)
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#define CONFIG_RED_LED 110
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#define CONFIG_GREEN_LED 109
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#define CONFIG_STM32_GPIO
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#define CONFIG_STM32_FLASH
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#define CONFIG_STM32_SERIAL
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#define CONFIG_STM32_HSE_HZ 8000000
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#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
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#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_MALLOC_LEN (2 << 20)
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#define CONFIG_BOOTCOMMAND \
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"run bootcmd_romfs"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
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"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
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"bootm 0x08044000 - 0x08042000\0"
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/*
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* Command line configuration.
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#endif /* __CONFIG_H */
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