/*
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* (C) Copyright 2009
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* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SPEAR_COMMON_H
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#define _SPEAR_COMMON_H
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/*
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* Common configurations used for both spear3xx as well as spear6xx
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*/
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/* U-Boot Load Address */
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#define CONFIG_SYS_TEXT_BASE 0x00700000
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/* Ethernet driver configuration */
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#define CONFIG_MII
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#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
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/* USBD driver configuration */
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#if defined(CONFIG_SPEAR_USBTTY)
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#define CONFIG_DW_UDC
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#define CONFIG_USB_DEVICE
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#define CONFIG_USBD_HS
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#define CONFIG_USB_TTY
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#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
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#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
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#endif
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#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
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/* I2C driver configuration */
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#define CONFIG_SYS_I2C
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#if defined(CONFIG_SPEAR600)
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#define CONFIG_SYS_I2C_BASE 0xD0200000
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#elif defined(CONFIG_SPEAR300)
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#define CONFIG_SYS_I2C_BASE 0xD0180000
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#elif defined(CONFIG_SPEAR310)
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#define CONFIG_SYS_I2C_BASE 0xD0180000
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#elif defined(CONFIG_SPEAR320)
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#define CONFIG_SYS_I2C_BASE 0xD0180000
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#endif
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#define CONFIG_SYS_I2C_SPEED 400000
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#define CONFIG_SYS_I2C_SLAVE 0x02
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#define CONFIG_I2C_CHIPADDRESS 0x50
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/* Timer, HZ specific defines */
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/* Flash configuration */
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#if defined(CONFIG_FLASH_PNOR)
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#define CONFIG_SPEAR_EMI
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#else
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#define CONFIG_ST_SMI
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#endif
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#if defined(CONFIG_ST_SMI)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BASE 0xF8000000
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#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
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#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
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#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_CS1_FLASH_BASE}
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
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#endif
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/*
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* Serial Configuration (PL011)
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* CONFIG_PL01x_PORTS is defined in specific files
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*/
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#define CONFIG_PL011_SERIAL
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#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
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#define CONFIG_CONS_INDEX 0
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
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57600, 115200 }
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/* NAND FLASH Configuration */
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_NAND_FSMC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/*
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* Default Environment Varible definitions
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*/
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#define CONFIG_ENV_OVERWRITE
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/*
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* U-Boot Environment placing definitions.
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*/
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#if defined(CONFIG_ENV_IS_IN_FLASH)
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#ifdef CONFIG_ST_SMI
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/*
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* Environment is in serial NOR flash
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*/
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#define CONFIG_SYS_MONITOR_LEN 0x00040000
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#define CONFIG_ENV_SECT_SIZE 0x00010000
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#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
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#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
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#elif defined(CONFIG_SPEAR_EMI)
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/*
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* Environment is in parallel NOR flash
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*/
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#define CONFIG_SYS_MONITOR_LEN 0x00060000
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#define CONFIG_ENV_SECT_SIZE 0x00020000
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#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
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#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
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"0x4C0000; bootm 0x1600000"
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#endif
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#elif defined(CONFIG_ENV_IS_IN_NAND)
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/*
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* Environment is in NAND
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*/
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_RANGE 0x10000
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#define CONFIG_FSMTDBLK "/dev/mtdblock7 "
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#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
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"0x80000 0x4C0000; " \
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"bootm 0x1600000"
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#endif
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#define CONFIG_NFSBOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):" \
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"$(netmask):$(hostname):$(netdev):off " \
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"console=ttyAMA0,115200 $(othbootargs);" \
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"bootm; "
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=ttyAMA0,115200 $(othbootargs);" \
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CONFIG_BOOTCOMMAND
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#define CONFIG_ENV_SIZE 0x02000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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/* Miscellaneous configurable options */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_MEMTEST_START 0x00800000
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#define CONFIG_SYS_MEMTEST_END 0x04000000
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#define CONFIG_SYS_MALLOC_LEN (1024*1024)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LOAD_ADDR 0x00800000
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x00000000
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#define PHYS_SDRAM_1_MAXSIZE 0x40000000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#endif
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