/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2010
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* Achim Ehrlich <aehrlich@taskit.de>
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* taskit GmbH <www.taskit.de>
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*
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* (C) Copyright 2012
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* Markus Hubig <mhubig@imko.de>
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* IMKO GmbH <www.imko.de>
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*
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* (C) Copyright 2014
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* Heiko Schocher <hs@denx.de>
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* DENX Software Engineering GmbH
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*
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* Configuation settings for the smartweb.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#include <linux/sizes.h>
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/*
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* Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
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* program. Since the linker has to swallow that define, we must use a pure
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* hex number here!
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*/
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#define CONFIG_SYS_TEXT_BASE 0x23000000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
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/* misc settings */
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#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
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#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
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#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
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#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */
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/* We set the max number of command args high to avoid HUSH bugs. */
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#define CONFIG_SYS_MAXARGS 32
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/* setting board specific options */
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#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_AUTOLOAD "yes"
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#define CONFIG_RESET_TO_RETRY
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/* The LED PINs */
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#define CONFIG_RED_LED AT91_PIN_PA9
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#define CONFIG_GREEN_LED AT91_PIN_PA6
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/*
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* SDRAM: 1 bank, 64 MB, base address 0x20000000
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* Already initialized before u-boot gets started.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
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/*
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* Perform a SDRAM Memtest from the start of SDRAM
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* till the beginning of the U-Boot position in RAM.
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*/
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN \
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ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000)
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/* NAND flash settings */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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#define CONFIG_AT91_GPIO /* enable the GPIO features */
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#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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/*
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* Ethernet configuration
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*
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*/
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#define CONFIG_MACB
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#define CONFIG_RMII /* use reduced MII inteface */
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#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
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#define CONFIG_AT91_WANTS_COMMON_PHY
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/* BOOTP and DHCP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv autoload yes; setenv autoboot yes; " \
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"setenv bootargs ${basicargs} ${mtdparts} " \
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"root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
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"dhcp"
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/* Enable the watchdog */
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#define CONFIG_AT91SAM9_WATCHDOG
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#if !defined(CONFIG_SPL_BUILD)
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#define CONFIG_HW_WATCHDOG
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#endif
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#define CONFIG_AT91_HW_WDT_TIMEOUT 15
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#if !defined(CONFIG_SPL_BUILD)
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/* USB configuration */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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/* USB DFU support */
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#define CONFIG_USB_GADGET_AT91
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/* DFU class support */
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#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
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#define DFU_MANIFEST_POLL_TIMEOUT 25000
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#endif
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/* General Boot Parameter */
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#define CONFIG_BOOTCOMMAND "run flashboot"
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#define CONFIG_SYS_CBSIZE 512
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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/*
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* RAM Memory address where to put the
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* Linux Kernel befor starting.
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x22000000
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/*
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* The NAND Flash partitions:
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*/
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#define CONFIG_ENV_OFFSET (0x100000)
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#define CONFIG_ENV_OFFSET_REDUND (0x180000)
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#define CONFIG_ENV_RANGE (SZ_512K)
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#define CONFIG_ENV_SIZE (SZ_128K)
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/*
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* Predefined environment variables.
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* Usefull to define some easy to use boot commands.
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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\
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"basicargs=console=ttyS0,115200\0" \
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\
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"mtdparts="MTDPARTS_DEFAULT"\0"
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x301000
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#define CONFIG_SPL_STACK_R
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#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE
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#else
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/*
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* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
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* leaving the correct space for initial global data structure above that
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* address while providing maximum stack area below.
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*/
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#define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#endif
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x0
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#define CONFIG_SPL_MAX_SIZE (SZ_4K)
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#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K)
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
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#define CONFIG_SYS_USE_NANDFLASH 1
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_RAW_ONLY
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_SIZE (SZ_256M)
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#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
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#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#define CONFIG_SPL_ATMEL_SIZE
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#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
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#define AT91_PLL_LOCK_TIMEOUT 1000000
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#define CONFIG_SYS_AT91_PLLA 0x2060bf09
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#define CONFIG_SYS_MCKR 0x100
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#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
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#define CONFIG_SYS_AT91_PLLB 0x10483f0e
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#if defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#endif
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#endif /* __CONFIG_H */
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