/*
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* Configuration settings for the SAMA5D2 PTC Engineering board.
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*
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* Copyright (C) 2016 Atmel
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* Wenyou Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "at91-sama5_common.h"
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_UART0
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#define CONFIG_USART_ID ATMEL_ID_UART0
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x210000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#undef CONFIG_AT91_GPIO
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#define CONFIG_ATMEL_PIO4
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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/* SerialFlash */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_ATMEL_SPI
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#endif
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* PMECC & PMERRLOC */
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#define CONFIG_ATMEL_NAND_HWECC
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#define CONFIG_ATMEL_NAND_HW_PMECC
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#endif
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/* USB device */
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/* Ethernet Hardware */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB_SEARCH_PHY
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#ifdef CONFIG_SYS_USE_NANDFLASH
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#undef CONFIG_ENV_OFFSET
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#undef CONFIG_ENV_OFFSET_REDUND
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#undef CONFIG_BOOTCOMMAND
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/* u-boot env in nand flash */
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#define CONFIG_ENV_OFFSET 0x200000
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#define CONFIG_ENV_OFFSET_REDUND 0x400000
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#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
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"nand read 0x22000000 0x600000 0x600000;" \
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"bootz 0x22000000 - 0x21000000"
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#endif
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/* SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x200000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#ifdef CONFIG_SYS_USE_SERIALFLASH
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
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#elif CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_PMECC_CAP 8
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#define CONFIG_PMECC_SECTOR_SIZE 512
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 224
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
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#endif
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#endif
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