/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3188_COMMON_H
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#define __CONFIG_RK3188_COMMON_H
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#include <asm/arch/hardware.h>
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#include "rockchip-common.h"
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#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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/* RK3188 do not have a ARMv7 ARCH timer */
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#undef CONFIG_SYS_ARCH_TIMER
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#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
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/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x60200000
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR 0x60400000
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#define CONFIG_SYS_LOAD_ADDR 0x60800800
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#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
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#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
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#define CONFIG_ROCKUSB_G_DNL_PID 0x310B
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#define CONFIG_SPL_TEXT_BASE 0x10080800
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/* spl size 32kb sram - 2kb bootrom */
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#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
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#define CONFIG_SPL_FRAMEWORK 1
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#define CONFIG_ROCKCHIP_SERIAL 1
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#define CONFIG_SPL_STACK 0x10087fff
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/* MMC/SD IP block */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define SDRAM_MAX_SIZE 0x80000000
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#ifndef CONFIG_SPL_BUILD
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/* usb mass storage */
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#define CONFIG_USB_FUNCTION_MASS_STORAGE
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/* usb otg */
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#define CONFIG_ROCKCHIP_USB2_PHY
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/* usb host support */
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x60000000\0" \
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"pxefile_addr_r=0x60100000\0" \
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"fdt_addr_r=0x68300000\0" \
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"kernel_addr_r=0x62000000\0" \
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"ramdisk_addr_r=0x6a200000\0"
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#include <config_distro_bootcmd.h>
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/* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
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* so limit the fdt reallocation to that */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x6fffffff\0" \
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"initrd_high=0x6fffffff\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_PREBOOT
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#endif
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