/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* This file contains the configuration parameters for the dbau1x00 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_PB1X00 1
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#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
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#ifdef CONFIG_PB1000
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#define CONFIG_SOC_AU1000 1
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#else
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#ifdef CONFIG_PB1100
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#define CONFIG_SOC_AU1100 1
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#else
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#ifdef CONFIG_PB1500
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#define CONFIG_SOC_AU1500 1
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#else
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#error "No valid board set"
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#endif
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#endif
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#endif
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"addmisc=setenv bootargs ${bootargs} " \
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"console=ttyS0,${baudrate} " \
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"panic=1\0" \
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"bootfile=/vmlinux.img\0" \
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"load=tftp 80500000 ${u-boot}\0" \
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""
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/* Boot from NFS root */
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#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_MALLOC_LEN 128*1024
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#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
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#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x80100000
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#undef CONFIG_SYS_MEMTEST_START
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#define CONFIG_SYS_MEMTEST_START 0x80200000
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#define CONFIG_SYS_MEMTEST_END 0x83800000
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (192 << 10)
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#define CONFIG_SYS_INIT_SP_OFFSET 0x4000000
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/* We boot from this flash, selected with dip switch */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/* Address and size of Primary Environment Sector */
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#define CONFIG_ENV_ADDR 0xB0030000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_FLASH_16BIT
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_MEMSIZE_IN_BYTES
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/*---USB -------------------------------------------*/
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#if 0
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#define CONFIG_USB_OHCI
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#endif
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/*---ATA PCMCIA ------------------------------------*/
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#if 0
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#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
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#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
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#define CONFIG_PCMCIA_SLOT_A
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#define CONFIG_ATAPI 1
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/* We run CF in "true ide" mode or a harddrive via pcmcia */
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#define CONFIG_IDE_PCMCIA 1
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/* We only support one slot for now */
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET 8
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET 0
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#endif /* __CONFIG_H */
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