/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the MX53ARD Freescale board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
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#include <asm/arch/imx-regs.h>
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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#define CONFIG_MXC_GPIO
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
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#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
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#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_MXC_NAND_HWECC
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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/* MMC Configs */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 2
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/* Eth Configs */
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#define CONFIG_HAS_ETH1
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#define CONFIG_MII
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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/* Command definition */
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#define CONFIG_ETHPRIME "smc911x"
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/*Support LAN9217*/
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_SMC911X_BASE CS1_BASE_ADDR
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#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
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#define CONFIG_SYS_TEXT_BASE 0x77800000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"uimage=zImage\0" \
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"console=ttymxc0\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"fdt_addr=0x78000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"update_sd_firmware_filename=u-boot.imx\0" \
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"update_sd_firmware=" \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"if mmc dev ${mmcdev}; then " \
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"if ${get_cmd} ${update_sd_firmware_filename}; then " \
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"setexpr fw_sz ${filesize} / 0x200; " \
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"setexpr fw_sz ${fw_sz} + 1; " \
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"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
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"fi; " \
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"fi\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${uimage}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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#define CONFIG_ARP_TIMEOUT 200UL
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MEMTEST_START 0x70000000
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#define CONFIG_SYS_MEMTEST_END 0x70010000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_CMDLINE_EDITING
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
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#define PHYS_SDRAM_2 CSD1_BASE_ADDR
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#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
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#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* environment organization */
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
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#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
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#define MX53ARD_CS1RCR2 RBEN(2)
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#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
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#endif /* __CONFIG_H */
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