/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the MX51EVK Board
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_TEXT_BASE 0x97800000
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#include <asm/arch/imx-regs.h>
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_FSL_IIM
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_MXC_GPIO
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/*
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* SPI Configs
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* */
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#define CONFIG_MXC_SPI
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/* PMIC Controller */
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#define CONFIG_POWER
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#define CONFIG_POWER_SPI
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#define CONFIG_POWER_FSL
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#define CONFIG_FSL_PMIC_BUS 0
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 2500000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/*
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* MMC Configs
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* */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
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#define CONFIG_SYS_FSL_ESDHC_NUM 2
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/*
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* Eth Configs
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*/
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#define CONFIG_MII
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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/* USB Configs */
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#define CONFIG_USB_EHCI_MX5
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#define CONFIG_MXC_USB_PORT 1
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#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
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#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
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/* Framebuffer and LCD */
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#define CONFIG_PREBOOT
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 133000000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_ETHPRIME "FEC0"
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#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=zImage\0" \
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"fdt_file=imx51-babbage.dtb\0" \
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"fdt_addr=0x91000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0" \
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"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${image}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo ERROR: Cannot load the DT; " \
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"exit; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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#define CONFIG_ARP_TIMEOUT 200UL
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MEMTEST_START 0x90000000
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#define CONFIG_SYS_MEMTEST_END 0x90010000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_CMDLINE_EDITING
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_DDR_CLKSEL 0
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#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
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#define CONFIG_SYS_MAIN_PWR_ON
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/*-----------------------------------------------------------------------
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* environment organization
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*/
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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