/*
|
* Copyright (C) 2014 Freescale Semiconductor
|
*
|
* SPDX-License-Identifier: GPL-2.0+
|
*/
|
|
#ifndef __LS2_SIMU_H
|
#define __LS2_SIMU_H
|
|
#include "ls2080a_common.h"
|
|
#define CONFIG_SYS_CLK_FREQ 100000000
|
#define CONFIG_DDR_CLK_FREQ 133333333
|
|
#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
|
#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
|
|
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
|
#endif
|
|
/* SMSC 91C111 ethernet configuration */
|
#define CONFIG_SMC91111
|
#define CONFIG_SMC91111_BASE (0x2210000)
|
|
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
|
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
|
#ifdef CONFIG_MTD_NOR_FLASH
|
#define CONFIG_FLASH_CFI_DRIVER
|
#define CONFIG_SYS_FLASH_CFI
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
#define CONFIG_SYS_FLASH_QUIET_TEST
|
#endif
|
|
/*
|
* NOR Flash Timing Params
|
*/
|
#define CONFIG_SYS_NOR0_CSPR \
|
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
CSPR_PORT_SIZE_16 | \
|
CSPR_MSEL_NOR | \
|
CSPR_V)
|
#define CONFIG_SYS_NOR0_CSPR_EARLY \
|
(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
|
CSPR_PORT_SIZE_16 | \
|
CSPR_MSEL_NOR | \
|
CSPR_V)
|
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
|
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
|
FTIM0_NOR_TEADC(0x1) | \
|
FTIM0_NOR_TEAHC(0x1))
|
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
|
FTIM1_NOR_TRAD_NOR(0x1))
|
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
|
FTIM2_NOR_TCH(0x0) | \
|
FTIM2_NOR_TWP(0x1))
|
#define CONFIG_SYS_NOR_FTIM3 0x04000000
|
#define CONFIG_SYS_IFC_CCR 0x01000000
|
|
#ifdef CONFIG_MTD_NOR_FLASH
|
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
#endif
|
|
#define CONFIG_NAND_FSL_IFC
|
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
|
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
| CSPR_V)
|
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
|
|
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
|
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
|
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
|
/* ONFI NAND Flash mode0 Timing Params */
|
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
|
FTIM0_NAND_TWP(0x18) | \
|
FTIM0_NAND_TWCHT(0x07) | \
|
FTIM0_NAND_TWH(0x0a))
|
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
FTIM1_NAND_TWBE(0x39) | \
|
FTIM1_NAND_TRR(0x0e) | \
|
FTIM1_NAND_TRP(0x18))
|
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
FTIM2_NAND_TREH(0x0a) | \
|
FTIM2_NAND_TWHRE(0x1e))
|
#define CONFIG_SYS_NAND_FTIM3 0x0
|
|
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
|
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
|
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
|
#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
|
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
|
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
|
/* MMC */
|
#ifdef CONFIG_MMC
|
#define CONFIG_FSL_ESDHC
|
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
#endif
|
|
/* Debug Server firmware */
|
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
|
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
|
|
/* MC firmware */
|
#define CONFIG_SYS_LS_MC_DPL_IN_NOR
|
#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
|
|
#define CONFIG_SYS_LS_MC_DPC_IN_NOR
|
#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
|
|
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
|
|
/* Store environment at top of flash */
|
#define CONFIG_ENV_SIZE 0x1000
|
|
#endif /* __LS2_SIMU_H */
|
