/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_DEEP_SLEEP
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(void);
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unsigned long get_board_ddr_clk(void);
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#endif
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define CONFIG_QIXIS_I2C_ACCESS
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#else
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#endif
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
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#endif
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#ifdef CONFIG_SD_BOOT
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#ifdef CONFIG_SD_BOOT_QSPI
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
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#else
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#define CONFIG_SYS_FSL_PBL_RCW \
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board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
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#endif
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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#define CONFIG_SYS_TEXT_BASE 0x82000000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0xc0000
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#endif
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_TEXT_BASE 0x40100000
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#endif
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SPL_PAD_TO 0x1c000
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#define CONFIG_SYS_TEXT_BASE 0x82000000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0x60100000
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#endif
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_DDR_SPD
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#define SPD_EEPROM_ADDRESS 0x51
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#ifndef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_DDR_RAW_TIMING
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#endif
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DDR_ECC
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
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!defined(CONFIG_QSPI_BOOT)
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#define CONFIG_U_QE
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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#endif
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/*
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
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+ 0x8000000) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
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CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
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/*
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* NAND Flash Definitions
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*/
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_NAND_BASE 0x7e800000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#endif
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/*
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* QIXIS Definitions
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*/
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#define CONFIG_FSL_QIXIS
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#ifdef CONFIG_FSL_QIXIS
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#define QIXIS_BASE 0x7fb00000
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_SWITCH 6
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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#define QIXIS_PWR_CTL 0x21
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#define QIXIS_PWR_CTL_POWEROFF 0x80
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#define QIXIS_RST_CTL_RESET 0x44
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_CTL_SYS 0x5
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#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
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#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
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#define QIXIS_RST_FORCE_3 0x45
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#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
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#define QIXIS_PWR_CTL2 0x21
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#define QIXIS_PWR_CTL2_PCTL 0x2
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#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
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#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/*
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* QIXIS Timing parameters for IFC GPCM
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*/
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#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
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FTIM0_GPCM_TEADC(0xe) | \
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FTIM0_GPCM_TEAHC(0xe))
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#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
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FTIM2_GPCM_TCH(0xe) | \
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FTIM2_GPCM_TWP(0xf0))
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#define CONFIG_SYS_FPGA_FTIM3 0x0
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#endif
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
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#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
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#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
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#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
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#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
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#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
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#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
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#endif
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/*
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* Serial Port
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*/
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#ifdef CONFIG_LPUART
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#define CONFIG_LPUART_32B_REG
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#else
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#endif
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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/*
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* I2C bus multiplexer
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH_CH7301 0xC
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/*
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* MMC
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*/
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#define CONFIG_FSL_ESDHC
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/* SPI */
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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/* QSPI */
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#define QSPI0_AMBA_BASE 0x40000000
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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/* DSPI */
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/* DM SPI */
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#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
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#define CONFIG_DM_SPI_FLASH
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#define CONFIG_SPI_FLASH_DATAFLASH
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#endif
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#endif
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/*
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* USB
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*/
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/* EHCI Support - disbaled by default */
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/*#define CONFIG_HAS_FSL_DR_USB*/
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#ifdef CONFIG_HAS_FSL_DR_USB
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#endif
|
|
/*XHCI Support - enabled by default*/
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_XHCI_FSL
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#endif
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/*
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* Video
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*/
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#ifdef CONFIG_VIDEO_FSL_DCU_FB
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_FSL_DIU_CH7301
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#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
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#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
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#define CONFIG_SYS_I2C_DVI_ADDR 0x75
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#endif
|
|
/*
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* eTSEC
|
*/
|
#define CONFIG_TSEC_ENET
|
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_MII
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#define CONFIG_MII_DEFAULT_TSEC 3
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
|
|
#define TSEC1_PHY_ADDR 1
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#define TSEC2_PHY_ADDR 2
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#define TSEC3_PHY_ADDR 3
|
|
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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|
#define CONFIG_ETHPRIME "eTSEC1"
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|
#define CONFIG_PHY_REALTEK
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_FSL_SGMII_RISER 1
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#define SGMII_RISER_PHY_OFFSET 0x1b
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|
#ifdef CONFIG_FSL_SGMII_RISER
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#define CONFIG_SYS_TBIPA_VALUE 8
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#endif
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#endif
|
|
/* PCIe */
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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|
#ifdef CONFIG_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_EDITING
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|
#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define COUNTER_FREQUENCY 12500000
|
|
#define CONFIG_HWCONFIG
|
#define HWCONFIG_BUFFER_SIZE 256
|
|
#define CONFIG_FSL_DEVICE_DISABLE
|
|
|
#define CONFIG_SYS_QE_FW_ADDR 0x60940000
|
|
#ifdef CONFIG_LPUART
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
|
"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
|
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
|
#else
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
|
"fdt_high=0xffffffff\0" \
|
"initrd_high=0xffffffff\0" \
|
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
|
#endif
|
|
/*
|
* Miscellaneous configurable options
|
*/
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
#define CONFIG_AUTO_COMPLETE
|
|
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
|
|
#define CONFIG_SYS_LOAD_ADDR 0x82000000
|
|
#define CONFIG_LS102XA_STREAM_ID
|
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
|
#ifdef CONFIG_SPL_BUILD
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
|
#else
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
#endif
|
|
/*
|
* Environment
|
*/
|
#define CONFIG_ENV_OVERWRITE
|
|
#if defined(CONFIG_SD_BOOT)
|
#define CONFIG_ENV_OFFSET 0x300000
|
#define CONFIG_SYS_MMC_ENV_DEV 0
|
#define CONFIG_ENV_SIZE 0x2000
|
#elif defined(CONFIG_QSPI_BOOT)
|
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
|
#define CONFIG_ENV_SECT_SIZE 0x10000
|
#elif defined(CONFIG_NAND_BOOT)
|
#define CONFIG_ENV_SIZE 0x2000
|
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
#else
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
|
#define CONFIG_ENV_SIZE 0x2000
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
#endif
|
|
#define CONFIG_MISC_INIT_R
|
|
#include <asm/fsl_secure_boot.h>
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
#endif
|
