/*
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* (C) Copyright 2013
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (c) 2011 IDS GmbH, Germany
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* Sergej Stepanov <ste@ids.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC831x
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#define CONFIG_MPC8313
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#define CONFIG_IDS8313
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#define CONFIG_FSL_ELBC
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#define CONFIG_MISC_INIT_R
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#define CONFIG_BOOT_RETRY_TIME 900
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#define CONFIG_BOOT_RETRY_MIN 30
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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#define CONFIG_SYS_IMMR 0xF0000000
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/*
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* Hardware Reset Configuration Word
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* if CLKIN is 66.000MHz, then
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* CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
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*/
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#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
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HRCWL_CSB_TO_CLKIN_2X1 |\
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HRCWL_CORE_TO_CSB_2X1)
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#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_8BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_MII |\
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HRCWH_TSEC2M_IN_MII |\
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HRCWH_BIG_ENDIAN)
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#define CONFIG_SYS_SICRH 0x00000000
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#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
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#define CONFIG_HWCONFIG
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
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HID0_ENABLE_INSTRUCTION_CACHE |\
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HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
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#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
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/*
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* Definitions for initial stack pointer and data area (in DCACHE )
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 0x100
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
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(0xFF << LBCR_BMT_SHIFT) |\
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0xF)
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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/*
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* Internal Definitions
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*/
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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/*
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* Manually set up DDR parameters,
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* as this board has not the SPD connected to I2C.
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*/
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
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0x00010000 |\
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CSCONFIG_ROW_BIT_13 |\
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CSCONFIG_COL_BIT_10)
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#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
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CSCONFIG_BANK_BIT_3)
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#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
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#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
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(3 << TIMING_CFG0_WRT_SHIFT) |\
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(3 << TIMING_CFG0_RRT_SHIFT) |\
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(3 << TIMING_CFG0_WWT_SHIFT) |\
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(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_MRS_CYC_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
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(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
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(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
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(7 << TIMING_CFG1_CASLAT_SHIFT) |\
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(4 << TIMING_CFG1_REFREC_SHIFT) |\
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(4 << TIMING_CFG1_WRREC_SHIFT) |\
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
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(2 << TIMING_CFG1_WRTORD_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
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(5 << TIMING_CFG2_CPO_SHIFT) |\
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
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(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
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(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
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(6 << TIMING_CFG2_FOUR_ACT_SHIFT))
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#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
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(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
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SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
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SDRAM_CFG_DBW_32 |\
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SDRAM_CFG_SDRAM_TYPE_DDR2)
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#define CONFIG_SYS_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
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(0x0242 << SDRAM_MODE_SD_SHIFT))
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
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DDRCDR_PZ_NOMZ |\
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DDRCDR_NZ_NOMZ |\
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DDRCDR_ODT |\
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DDRCDR_M_ODR |\
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DDRCDR_Q_DRN)
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/*
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* on-board devices
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*/
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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#define CONFIG_TSEC_ENET
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#define CONFIG_HARD_SPI
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/*
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* NOR FLASH setup
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_FLASH_SHOW_PROGRESS 50
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_FLASH_SIZE 8
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
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BR_PS_8 |\
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BR_MS_GPCM |\
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BR_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
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OR_GPCM_SCY_10 |\
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OR_GPCM_EHTR |\
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OR_GPCM_TRLX |\
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OR_GPCM_CSNT |\
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OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/*
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* NAND FLASH setup
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*/
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#define CONFIG_SYS_NAND_BASE 0xE1000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
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#define NAND_CACHE_PAGES 64
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
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#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
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#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
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(2<<BR_DECC_SHIFT) |\
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BR_PS_8 |\
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BR_MS_FCM |\
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BR_V)
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#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
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OR_FCM_PGS |\
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OR_FCM_CSCT |\
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OR_FCM_CST |\
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OR_FCM_CHT |\
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OR_FCM_SCY_4 |\
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OR_FCM_TRLX |\
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OR_FCM_EHTR |\
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OR_FCM_RST)
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/*
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* MRAM setup
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*/
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#define CONFIG_SYS_MRAM_BASE 0xE2000000
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#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
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#define CONFIG_SYS_OR_TIMING_MRAM
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
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BR_PS_8 |\
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BR_MS_GPCM |\
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
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/*
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* CPLD setup
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*/
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#define CONFIG_SYS_CPLD_BASE 0xE3000000
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#define CONFIG_SYS_CPLD_SIZE 0x8000
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
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#define CONFIG_SYS_OR_TIMING_MRAM
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
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BR_PS_8 |\
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BR_MS_GPCM |\
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
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/*
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* HW-Watchdog
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*/
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#define CONFIG_WATCHDOG 1
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#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
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/*
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* I2C setup
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* SPI setup
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*/
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#ifdef CONFIG_HARD_SPI
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#define CONFIG_SYS_GPIO1_PRELIM
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#define CONFIG_SYS_GPIO1_DIR 0x00000001
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#define CONFIG_SYS_GPIO1_DAT 0x00000001
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#endif
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/*
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* Ethernet setup
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*/
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x1
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC1_PHYIDX 0
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#endif
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define TSEC2_PHY_ADDR 0x3
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC2_PHYIDX 0
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#endif
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#define CONFIG_ETHPRIME "TSEC1"
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
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#define CONFIG_HAS_FSL_DR_USB
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#define CONFIG_SYS_SCCR_USBDRCM 3
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/*
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* BAT's
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*/
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#define CONFIG_HIGH_BATS
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/* DDR @ 0x00000000 */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
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BATL_PP_10)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
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BATU_BL_256M |\
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BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* Initial RAM @ 0xFD000000 */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
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BATL_PP_10 |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
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BATU_BL_256K |\
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BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* FLASH @ 0xFF800000 */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
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BATL_PP_10 |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
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BATU_BL_8M |\
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BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
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BATL_PP_10 |\
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BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_IBAT3L (0)
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#define CONFIG_SYS_IBAT3U (0)
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_IBAT4L (0)
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#define CONFIG_SYS_IBAT4U (0)
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/* IMMRBAR @ 0xF0000000 */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
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BATL_PP_10 |\
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BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
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BATU_BL_128M |\
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BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
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#define CONFIG_SYS_IBAT6L (0xE0000000 |\
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BATL_PP_10 |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (0xE0000000 |\
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BATU_BL_256M |\
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BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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/*
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* U-Boot environment setup
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*/
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
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+ CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#define CONFIG_NETDEV eth1
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#define CONFIG_HOSTNAME ids8313
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#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
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#define CONFIG_BOOTFILE "ids8313/uImage"
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#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
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#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
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#define CONFIG_LOADADDR 0x400000
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#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
|
|
/* Initial Memory map for Linux*/
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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|
/*
|
* Miscellaneous configurable options
|
*/
|
#define CONFIG_SYS_LONGHELP
|
#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
#define CONFIG_SYS_MEMTEST_START 0x00001000
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#define CONFIG_SYS_MEMTEST_END 0x00C00000
|
|
#define CONFIG_SYS_LOAD_ADDR 0x100000
|
#define CONFIG_MII
|
#define CONFIG_LOADS_ECHO
|
#define CONFIG_TIMESTAMP
|
#define CONFIG_PREBOOT "echo;" \
|
"echo Type \\\"run nfsboot\\\" " \
|
"to mount root filesystem over NFS;echo"
|
#define CONFIG_BOOTCOMMAND "run boot_cramfs"
|
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
|
#define CONFIG_JFFS2_NAND
|
#define CONFIG_JFFS2_DEV "0"
|
|
/* mtdparts command line support */
|
#define CONFIG_FLASH_CFI_MTD
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=" __stringify(CONFIG_NETDEV) "\0" \
|
"ethprime=TSEC1\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
"tftpflash=tftpboot ${loadaddr} ${uboot}; " \
|
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
" +${filesize}; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
" +${filesize}; " \
|
"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
|
" ${filesize}; " \
|
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
" +${filesize}; " \
|
"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
|
" ${filesize}\0" \
|
"console=ttyS0\0" \
|
"fdtaddr=0x780000\0" \
|
"kernel_addr=ff800000\0" \
|
"fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
|
"setbootargs=setenv bootargs " \
|
"root=${rootdev} rw console=${console}," \
|
"${baudrate} ${othbootargs}\0" \
|
"setipargs=setenv bootargs root=${rootdev} rw " \
|
"nfsroot=${serverip}:${rootpath} " \
|
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
"${netmask}:${hostname}:${netdev}:off " \
|
"console=${console},${baudrate} ${othbootargs}\0" \
|
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
"mtdids=" MTDIDS_DEFAULT "\0" \
|
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
"\0"
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
"setenv rootdev /dev/nfs;" \
|
"run setipargs;run addmtd;" \
|
"tftp ${loadaddr} ${bootfile};" \
|
"tftp ${fdtaddr} ${fdtfile};" \
|
"fdt addr ${fdtaddr};" \
|
"bootm ${loadaddr} - ${fdtaddr}"
|
|
/* UBI Support */
|
|
/* bootcount support */
|
#define CONFIG_BOOTCOUNT_LIMIT
|
#define CONFIG_BOOTCOUNT_I2C
|
#define CONFIG_BOOTCOUNT_ALEN 1
|
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
|
|
#define CONFIG_IMAGE_FORMAT_LEGACY
|
|
#endif /* __CONFIG_H */
|
