/*
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* Copyright (C) 2011-2014 OMICRON electronics GmbH
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*
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* Based on da850evm.h. Original Copyrights follow:
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
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/*
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* SoC Configuration
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*/
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#define CONFIG_MACH_DAVINCI_CALIMAIN
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#define CONFIG_DA850_LOWLEVEL
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
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#define CONFIG_SYS_WDT_PERIOD_LOW \
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(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
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#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
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#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
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/*
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* PLL configuration
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*/
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#define CONFIG_SYS_DV_CLKMODE 0
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLM \
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((calimain_get_osc_freq() == 25000000) ? 23 : 24)
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#define CONFIG_SYS_DA850_PLL1_PLLM \
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((calimain_get_osc_freq() == 25000000) ? 20 : 21)
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/*
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* DDR2 memory configuration
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*/
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
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(0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
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(16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(7 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(2 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
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/*
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* Flash memory timing
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*/
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#define CONFIG_SYS_DA850_CS2CFG ( \
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DAVINCI_ABCR_WSETUP(2) | \
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DAVINCI_ABCR_WSTROBE(5) | \
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DAVINCI_ABCR_WHOLD(3) | \
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DAVINCI_ABCR_RSETUP(1) | \
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DAVINCI_ABCR_RSTROBE(14) | \
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DAVINCI_ABCR_RHOLD(0) | \
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DAVINCI_ABCR_TA(3) | \
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DAVINCI_ABCR_ASIZE_16BIT)
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/* single 64 MB NOR flash device connected to CS2 and CS3 */
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#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
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/*
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* Memory Info
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*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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/*
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* Serial Driver info
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
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#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
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#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
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#define CONFIG_ENV_SIZE (128 << 10)
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
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#define CONFIG_SYS_MAX_FLASH_SECT \
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((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
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/*
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* Network & Ethernet Configuration
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*/
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#endif
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/*
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* U-Boot general configuration
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*/
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
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#define CONFIG_LOADADDR 0xc0700000
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_MX_CYCLIC
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/*
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* Linux Information
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*/
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#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
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#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
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#define CONFIG_RESET_TO_RETRY
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/*
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* Default environment settings
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* gpio0 = button, gpio1 = led green, gpio2 = led red
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* verify = n ... disable kernel checksum verification for faster booting
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"tftpdir=calimero\0" \
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"flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
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"erase 0x60800000 +0x400000; " \
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"cp.b $loadaddr 0x60800000 $filesize\0" \
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"flashrootfs=" \
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"tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
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"erase 0x60c00000 +0x2e00000; " \
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"cp.b $loadaddr 0x60c00000 $filesize\0" \
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"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
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"protect off all; " \
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"erase 0x60000000 +0x80000; " \
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"cp.b $loadaddr 0x60000000 $filesize\0" \
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"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
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"erase 0x60080000 +0x780000; " \
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"cp.b $loadaddr 0x60080000 $filesize\0" \
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"erase_persistent=erase 0x63a00000 +0x600000;\0" \
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"bootnor=setenv bootargs console=ttyS2,115200n8 " \
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"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
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"rootwait ethaddr=$ethaddr; " \
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"gpio c 1; gpio s 2; bootm 0x60800000\0" \
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"bootrlk=gpio s 1; gpio s 2;" \
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"setenv bootargs console=ttyS2,115200n8 " \
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"ethaddr=$ethaddr; bootm 0x60080000\0" \
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"boottftp=setenv bootargs console=ttyS2,115200n8 " \
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"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
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"rootwait ethaddr=$ethaddr; " \
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"tftpboot $loadaddr $tftpdir/uImage;" \
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"gpio c 1; gpio s 2; bootm $loadaddr\0" \
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"checkupdate=if test -n $update_flag; then " \
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"echo Previous update failed - starting RLK; " \
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"run bootrlk; fi; " \
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"if test -n $initial_setup; then " \
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"echo Running initial setup procedure; " \
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"sleep 1; run flashall; fi\0" \
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"product=accessory\0" \
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"serial=XX12345\0" \
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"checknor=" \
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"if gpio i 0; then run bootnor; fi;\0" \
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"checkrlk=" \
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"if gpio i 0; then run bootrlk; fi;\0" \
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"checkbutton=" \
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"run checknor; sleep 1;" \
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"run checknor; sleep 1;" \
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"run checknor; sleep 1;" \
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"run checknor; sleep 1;" \
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"run checknor;" \
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"gpio s 1; gpio s 2;" \
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"echo ---- Release button to boot RLK ----;" \
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"run checkrlk; sleep 1;" \
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"run checkrlk; sleep 1;" \
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"run checkrlk; sleep 1;" \
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"run checkrlk; sleep 1;" \
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"run checkrlk; sleep 1;" \
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"run checkrlk;" \
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"echo ---- Factory reset requested ----;" \
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"gpio c 1;" \
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"setenv factory_reset true;" \
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"saveenv;" \
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"run bootnor;\0" \
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"flashall=run flashrlk;" \
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"run flashkernel;" \
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"run flashrootfs;" \
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"setenv erase_datafs true;" \
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"setenv initial_setup;" \
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"saveenv;" \
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"run bootnor;\0" \
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"verify=n\0" \
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"clearenv=protect off all;" \
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"erase 0x60040000 +0x40000;\0" \
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"bootlimit=3\0" \
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"altbootcmd=run bootrlk\0"
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#define CONFIG_PREBOOT \
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"echo Version: $ver; " \
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"echo Serial: $serial; " \
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"echo MAC: $ethaddr; " \
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"echo Product: $product; " \
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"gpio c 1; gpio c 2;"
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/* additions for new relocation code, must added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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/* initial stack pointer in internal SRAM */
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#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
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#define CONFIG_BOOTCOUNT_LIMIT
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#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
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#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
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#ifndef __ASSEMBLY__
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int calimain_get_osc_freq(void);
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#endif
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#include <asm/arch/hardware.h>
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#endif /* __CONFIG_H */
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