/*
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* Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_AXS10X_H_
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#define _CONFIG_AXS10X_H_
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#include <linux/sizes.h>
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/*
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* CPU configuration
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*/
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#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
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#define ARC_APB_PERIPHERAL_BASE 0xF0000000
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#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
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#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
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/*
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* Memory configuration
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE SZ_512M
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_MALLOC_LEN SZ_2M
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#define CONFIG_SYS_BOOTM_LEN SZ_32M
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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/*
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* This board might be of different versions so handle it
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*/
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#define CONFIG_BOARD_TYPES
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/*
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* NAND Flash configuration
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*/
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#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/*
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* UART configuration
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*/
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#define CONFIG_DW_SERIAL
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK 33333333
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#define CONFIG_SYS_NS16550_MEM32
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/*
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* Ethernet PHY configuration
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*/
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#define CONFIG_MII
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/*
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* USB 1.1 configuration
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*/
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_SIZE SZ_16K
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/*
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* Environment configuration
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*/
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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/*
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* Console configuration
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*/
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#define CONFIG_SYS_LONGHELP
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/*
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* Misc utility configuration
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*/
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#define CONFIG_BOUNCE_BUFFER
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#endif /* _CONFIG_AXS10X_H_ */
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