/*
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* (C) Copyright 2015
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* (C) Copyright 2014
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX6Q SabreSD board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARISTAINETOS_COMMON_CONFIG_H
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#define __ARISTAINETOS_COMMON_CONFIG_H
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#include "mx6_common.h"
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#define CONFIG_MACH_TYPE 4501
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#define CONFIG_MMCROOT "/dev/mmcblk0p1"
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
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#define CONFIG_MXC_UART
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_SPI_FLASH_MTD
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#define CONFIG_MXC_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=u-boot.scr\0" \
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"fit_file=/boot/system.itb\0" \
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"loadaddr=0x12000000\0" \
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"fit_addr_r=0x14000000\0" \
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"uboot=/boot/u-boot.imx\0" \
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"uboot_sz=d0000\0" \
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"rescue_sys_addr=f0000\0" \
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"rescue_sys_length=f10000\0" \
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"panel=lb07wv8\0" \
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"splashpos=m,m\0" \
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"console=" CONSOLE_DEV "\0" \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
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"default ${board_type}\0" \
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"get_env=mw ${loadaddr} 0 0x20000;" \
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"mmc rescan;" \
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"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
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"env import -t ${loadaddr}\0" \
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"default_env=mw ${loadaddr} 0 0x20000;" \
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"env export -t ${loadaddr} serial# ethaddr eth1addr " \
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"board_type panel;" \
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"env default -a;" \
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"env import -t ${loadaddr}\0" \
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"loadbootscript=" \
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"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"mmcpart=1\0" \
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"mmcdev=0\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs addmtd addmisc set_fit_default;" \
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"bootm ${fit_addr_r}\0" \
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"mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
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"${fit_file}\0" \
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"mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
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"${uboot}\0" \
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"mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
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"setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
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"setexpr uboot_maxsize ${uboot_sz} - 400;" \
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"mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
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"run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
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"sf write ${loadaddr} 400 ${filesize};" \
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"sf read ${cmp_buf} 400 ${uboot_sz};" \
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"cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
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"ubiboot=echo Booting from ubi ...; " \
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"run ubiargs addmtd addmisc set_fit_default;" \
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"bootm ${fit_addr_r}\0" \
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"rescueargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/ram rw\0 " \
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"rescueboot=echo Booting rescue system from NOR ...; " \
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"run rescueargs addmtd addmisc set_fit_default;" \
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"bootm ${fit_addr_r}\0" \
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"rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
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"${rescue_sys_length}; imi ${fit_addr_r}\0" \
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CONFIG_EXTRA_ENV_BOARD_SETTINGS
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev};" \
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"if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run mmc_load_fit; then " \
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"run mmcboot; " \
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"else " \
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"if run ubifs_load_fit; then " \
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"run ubiboot; " \
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"else " \
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"if run rescue_load_fit; then " \
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"run rescueboot; " \
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"else " \
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"echo RESCUE SYSTEM BOOT " \
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"FAILURE;" \
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"fi; " \
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"fi; " \
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"fi; " \
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"fi; " \
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"else " \
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"if run ubifs_load_fit; then " \
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"run ubiboot; " \
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"else " \
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"if run rescue_load_fit; then " \
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"run rescueboot; " \
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"else " \
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"echo RESCUE SYSTEM BOOT FAILURE;" \
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"fi; " \
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"fi; " \
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"fi"
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#define CONFIG_ARP_TIMEOUT 200UL
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Environment organization */
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#define CONFIG_ENV_SIZE (12 * 1024)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
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#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
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#define CONFIG_ENV_SECT_SIZE (0x010000)
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#define CONFIG_ENV_OFFSET (0x0d0000)
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#define CONFIG_ENV_OFFSET_REDUND (0x0e0000)
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x7f
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
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/* NAND stuff */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* DMA stuff, needed for GPMI/MXS NAND support */
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/* RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_RTC_BUS_NUM 2
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#define CONFIG_RTC_M41T11
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/* USB Configs */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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/* UBI support */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_IMX_WATCHDOG
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/* Framebuffer */
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#define CONFIG_VIDEO_IPUV3
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/* check this console not needed, after test remove it */
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IPUV3_CLK 198000000
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#define CONFIG_IMX_VIDEO_SKIP
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#define CONFIG_PWM_IMX
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#define CONFIG_IMX6_PWM_PER_CLK 66000000
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#endif /* __ARISTAINETOS_COMMON_CONFIG_H */
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