/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* T1024/T1023 QDS board configuration file
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*/
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#ifndef __T1024QDS_H
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#define __T1024QDS_H
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/* High Level Configuration Options */
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#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_DEEP_SLEEP
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_MAX_SIZE 0x28000
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#define RESET_VECTOR_OFFSET 0x27FFC
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#define BOOT_PAGE_OFFSET 0x27000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_SKIP_RELOCATE
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
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#define CONFIG_SPL_NAND_BOOT
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#endif
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
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#define CONFIG_SPL_SPI_BOOT
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
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#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#endif
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
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#define CONFIG_SPL_MMC_BOOT
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#endif
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#endif /* CONFIG_RAMBOOT_PBL */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifdef CONFIG_MTD_NOR_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#endif
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/* PCIe Boot - Master */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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/*
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* for slave u-boot IMAGE instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
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#else
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
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#endif
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/*
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* for slave UCODE and ENV instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
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#else
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
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#endif
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
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/* slave core release by master*/
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#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
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#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
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/* PCIe Boot - Slave */
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
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/* Set 1M boot space for PCIe boot */
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#if defined(CONFIG_SPIFLASH)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#elif defined(CONFIG_SDCARD)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (512 * 0x800)
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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#define CONFIG_ENV_ADDR 0xffe20000
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#define CONFIG_ENV_SIZE 0x2000
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#elif defined(CONFIG_ENV_IS_NOWHERE)
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(void);
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unsigned long get_board_ddr_clk(void);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_SYS_CACHE_STASHING
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#define CONFIG_BACKSIDE_L2_CACHE
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#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_DDR_ECC
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_SYS_ALT_MEMTEST
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
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#define CONFIG_SYS_L3_SIZE (256 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
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#endif
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
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#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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#endif
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x51
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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/*
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* IFC Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
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+ 0x8000000) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
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#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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/* NOR Flash Timing Params */
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#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1A) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0x0
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
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+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_FSL_QIXIS /* use common QIXIS code */
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#define QIXIS_BASE 0xffdf0000
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#ifdef CONFIG_PHYS_64BIT
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#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
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#else
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#endif
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#define QIXIS_LBMAP_SWITCH 0x06
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_RST_FORCE_MEM 0x01
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#define CONFIG_SYS_CSPR3_EXT (0xf)
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#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
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#define CONFIG_SYS_CSOR3 0x0
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/* QIXIS Timing parameters for IFC CS3 */
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#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
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FTIM2_GPCM_TCH(0x8) | \
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FTIM2_GPCM_TWP(0x1f))
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#define CONFIG_SYS_CS3_FTIM3 0x0
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_NAND_BASE 0xff800000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* ONFI NAND Flash mode0 Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_DDR_LAW 11
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#if defined(CONFIG_NAND)
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#endif
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#if defined(CONFIG_RAMBOOT_PBL)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_HWCONFIG
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
#else
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
#endif
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
GENERATED_GBL_DATA_SIZE)
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
|
/* Serial Port */
|
#define CONFIG_CONS_INDEX 1
|
#define CONFIG_SYS_NS16550_SERIAL
|
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
|
#define CONFIG_SYS_BAUDRATE_TABLE \
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
|
/* Video */
|
#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */
|
#define CONFIG_FSL_DIU_FB
|
#ifdef CONFIG_FSL_DIU_FB
|
#define CONFIG_FSL_DIU_CH7301
|
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
|
#define CONFIG_VIDEO_LOGO
|
#define CONFIG_VIDEO_BMP_LOGO
|
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
|
/*
|
* With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
|
* disable empty flash sector detection, which is I/O-intensive.
|
*/
|
#undef CONFIG_SYS_FLASH_EMPTY_INFO
|
#endif
|
#endif
|
|
/* I2C */
|
#define CONFIG_SYS_I2C
|
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
|
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
|
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
|
#define I2C_MUX_PCA_ADDR 0x77
|
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
|
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
|
#define I2C_RETIMER_ADDR 0x18
|
|
/* I2C bus multiplexer */
|
#define I2C_MUX_CH_DEFAULT 0x8
|
#define I2C_MUX_CH_DIU 0xC
|
#define I2C_MUX_CH5 0xD
|
#define I2C_MUX_CH7 0xF
|
|
/* LDI/DVI Encoder for display */
|
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
|
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
|
|
/*
|
* RTC configuration
|
*/
|
#define RTC
|
#define CONFIG_RTC_DS3231 1
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
|
/*
|
* eSPI - Enhanced SPI
|
*/
|
#ifndef CONFIG_SPL_BUILD
|
#endif
|
#define CONFIG_SPI_FLASH_BAR
|
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
#define CONFIG_SF_DEFAULT_MODE 0
|
|
/*
|
* General PCIe
|
* Memory space is mapped 1-1, but I/O space must start from 0.
|
*/
|
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
#define CONFIG_PCIE3 /* PCIE controller 3 */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_PCI_INDIRECT_BRIDGE
|
|
#ifdef CONFIG_PCI
|
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
#ifdef CONFIG_PCIE1
|
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
#else
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
#endif
|
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
#else
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
|
#endif
|
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
#endif
|
|
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
#ifdef CONFIG_PCIE2
|
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
|
#else
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
|
#endif
|
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
#else
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
|
#endif
|
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
#endif
|
|
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
#ifdef CONFIG_PCIE3
|
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
|
#else
|
#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
|
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
|
#endif
|
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
#else
|
#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
|
#endif
|
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
#endif
|
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#endif /* CONFIG_PCI */
|
|
/*
|
*SATA
|
*/
|
#define CONFIG_FSL_SATA_V2
|
#ifdef CONFIG_FSL_SATA_V2
|
#define CONFIG_LIBATA
|
#define CONFIG_FSL_SATA
|
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
#define CONFIG_SATA1
|
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
#define CONFIG_LBA48
|
#endif
|
|
/*
|
* USB
|
*/
|
#define CONFIG_HAS_FSL_DR_USB
|
|
#ifdef CONFIG_HAS_FSL_DR_USB
|
#define CONFIG_USB_EHCI_FSL
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
#endif
|
|
/*
|
* SDHC
|
*/
|
#ifdef CONFIG_MMC
|
#define CONFIG_FSL_ESDHC
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
#endif
|
|
/* Qman/Bman */
|
#ifndef CONFIG_NOBQFMAN
|
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
#else
|
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
#endif
|
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
CONFIG_SYS_BMAN_CENA_SIZE)
|
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
#ifdef CONFIG_PHYS_64BIT
|
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
#else
|
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
#endif
|
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
CONFIG_SYS_QMAN_CENA_SIZE)
|
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
|
#define CONFIG_SYS_DPAA_FMAN
|
|
#define CONFIG_QE
|
#define CONFIG_U_QE
|
/* Default address of microcode for the Linux FMan driver */
|
#if defined(CONFIG_SPIFLASH)
|
/*
|
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
* env, so we got 0x110000.
|
*/
|
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
|
#define CONFIG_SYS_QE_FW_ADDR 0x130000
|
#elif defined(CONFIG_SDCARD)
|
/*
|
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
|
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
|
*/
|
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
|
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
|
#elif defined(CONFIG_NAND)
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
|
/*
|
* Slave has no ucode locally, it can fetch this from remote. When implementing
|
* in two corenet boards, slave's ucode could be stored in master's memory
|
* space, the address can be mapped from slave TLB->slave LAW->
|
* slave SRIO or PCIE outbound window->master inbound window->
|
* master LAW->the ucode address in master's memory space.
|
*/
|
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
|
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
|
#else
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
|
#endif
|
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
#endif /* CONFIG_NOBQFMAN */
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
#define CONFIG_FMAN_ENET
|
#define CONFIG_PHYLIB_10G
|
#define CONFIG_PHY_VITESSE
|
#define CONFIG_PHY_REALTEK
|
#define CONFIG_PHY_TERANETICS
|
#define RGMII_PHY1_ADDR 0x1
|
#define RGMII_PHY2_ADDR 0x2
|
#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
|
#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
|
#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
|
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
|
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
#endif
|
|
#ifdef CONFIG_FMAN_ENET
|
#define CONFIG_MII /* MII PHY management */
|
#define CONFIG_ETHPRIME "FM1@DTSEC4"
|
#endif
|
|
/*
|
* Dynamic MTD Partition support with mtdparts
|
*/
|
#ifdef CONFIG_MTD_NOR_FLASH
|
#define CONFIG_FLASH_CFI_MTD
|
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
|
"spi0=spife110000.0"
|
#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
|
"128k(dtb),96m(fs),-(user);"\
|
"fff800000.flash:2m(uboot),9m(kernel),"\
|
"128k(dtb),96m(fs),-(user);spife110000.0:" \
|
"2m(uboot),9m(kernel),128k(dtb),-(user)"
|
#endif
|
|
/*
|
* Environment
|
*/
|
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
|
/*
|
* Miscellaneous configurable options
|
*/
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
/*
|
* For booting Linux, the board info and command line data
|
* have to be in the first 64 MB of memory, since this is
|
* the maximum mapped by the Linux kernel during initialization.
|
*/
|
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
#ifdef CONFIG_CMD_KGDB
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
#endif
|
|
/*
|
* Environment Configuration
|
*/
|
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
#define CONFIG_BOOTFILE "uImage"
|
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
|
#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
|
#define __USB_PHY_TYPE utmi
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
"hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
|
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
|
"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
|
"ramdiskfile=t1024qds/ramdisk.uboot\0" \
|
"fdtfile=t1024qds/t1024qds.dtb\0" \
|
"netdev=eth0\0" \
|
"video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
|
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
"tftpflash=tftpboot $loadaddr $uboot && " \
|
"protect off $ubootaddr +$filesize && " \
|
"erase $ubootaddr +$filesize && " \
|
"cp.b $loadaddr $ubootaddr $filesize && " \
|
"protect on $ubootaddr +$filesize && " \
|
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
"consoledev=ttyS0\0" \
|
"ramdiskaddr=2000000\0" \
|
"fdtaddr=d00000\0" \
|
"bdev=sda3\0"
|
|
#define CONFIG_LINUX \
|
"setenv bootargs root=/dev/ram rw " \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
"setenv ramdiskaddr 0x02000000;" \
|
"setenv fdtaddr 0x00c00000;" \
|
"setenv loadaddr 0x1000000;" \
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
"setenv bootargs root=/dev/nfs rw " \
|
"nfsroot=$serverip:$rootpath " \
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
"tftp $loadaddr $bootfile;" \
|
"tftp $fdtaddr $fdtfile;" \
|
"bootm $loadaddr - $fdtaddr"
|
|
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
|
|
#include <asm/fsl_secure_boot.h>
|
|
#endif /* __T1024QDS_H */
|
