/*
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* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* mpc8548cds board configuration file
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*
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* Please refer to doc/README.mpc85xxcds for more info.
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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#endif
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_PCI1 /* PCI controller 1 */
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#undef CONFIG_PCI2
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_VIA
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_SYS_CCSRBAR 0xe0000000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#define CONFIG_DDR_SPD
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
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/* Make sure required options are set */
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#ifndef CONFIG_SPD_EEPROM
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#error ("CONFIG_SPD_EEPROM is required")
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Physical Address Map
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*
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* 32bit:
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* 0x0000_0000 0x7fff_ffff DDR 2G cacheable
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
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* 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
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* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
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* 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
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* 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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* 36bit:
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* 0x00000_0000 0x07fff_ffff DDR 2G cacheable
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* 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
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* 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
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* 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
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* 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
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* 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
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* 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
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* 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
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* 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
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* 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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*/
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/*
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* Local Bus Definitions
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*/
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/*
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* FLASH on the Local Bus
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* Two banks, 8M each, using the CFI driver.
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* Boot from BR0/OR0 bank at 0xff00_0000
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* Alternate BR1/OR1 bank at 0xff80_0000
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*
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* BR0, BR1:
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* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
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* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
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* Port Size = 16 bits = BRx[19:20] = 10
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* Use GPCM = BRx[24:26] = 000
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* Valid = BRx[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
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* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
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*
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* OR0, OR1:
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* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
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* Reserved ORx[17:18] = 11, confusion here?
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* CSNT = ORx[20] = 1
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* ACS = half cycle delay = ORx[21:22] = 11
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* SCY = 6 = ORx[24:27] = 0110
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* TRLX = use relaxed timing = ORx[29] = 1
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* EAD = use external address latch delay = OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
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*/
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_BR0_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_BR1_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM 0xff806e65
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#define CONFIG_SYS_OR1_PRELIM 0xff806e65
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_HWCONFIG /* enable hwconfig */
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/*
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* SDRAM on the Local Bus
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*/
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
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#else
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#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
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#endif
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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/*
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* Base Register 2 and Option Register 2 configure SDRAM.
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* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
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*
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* For BR2, need:
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* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
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* port-size = 32-bits = BR2[19:20] = 11
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* no parity checking = BR2[21:22] = 00
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* SDRAM for MSEL = BR2[24:26] = 011
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
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*
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* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
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* FIXME: the top 17 bits of BR2.
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*/
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#define CONFIG_SYS_BR2_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
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| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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*
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* For OR2, need:
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* 64MB mask for AM, OR2[0:7] = 1111 1100
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* XAM, OR2[17:18] = 11
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* 9 columns OR2[19-21] = 010
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* 13 rows OR2[23-25] = 100
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* EAD set for extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
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*/
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
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#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
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#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
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/*
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* Common settings for all Local Bus SDRAM commands.
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* At run time, either BSMA1516 (for CPU 1.1)
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* or BSMA1617 (for CPU 1.0) (old)
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* is OR'ed in too.
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*/
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#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
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| LSDMR_PRETOACT7 \
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| LSDMR_ACTTORW7 \
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| LSDMR_BL8 \
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| LSDMR_WRC4 \
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| LSDMR_CL3 \
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| LSDMR_RFEN \
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)
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/*
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* The CADMUS registers are connected to CS3 on CDS.
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* The new memory map places CADMUS at 0xf8000000.
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*
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* For BR3, need:
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* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
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* port-size = 8-bits = BR[19:20] = 01
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* no parity checking = BR[21:22] = 00
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* GPMC for MSEL = BR[24:26] = 000
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
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*
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* For OR3, need:
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* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
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* disable buffer ctrl OR[19] = 0
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* CSNT OR[20] = 1
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* ACS OR[21:22] = 11
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* XACS OR[23] = 1
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* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
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* SETA OR[28] = 0
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* TRLX OR[29] = 1
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* EHTR OR[30] = 1
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* EAD extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
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*/
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#define CONFIG_FSL_CADMUS
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#define CADMUS_BASE_ADDR 0xf8000000
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#ifdef CONFIG_PHYS_64BIT
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#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
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#else
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#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
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#endif
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#define CONFIG_SYS_BR3_PRELIM \
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(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_CCID
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#define CONFIG_SYS_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
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#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
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#else
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#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
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#endif
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#ifdef CONFIG_PCIE1
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#define CONFIG_SYS_PCIE1_NAME "Slot"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
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#endif
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/*
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* RapidIO MMU
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
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#ifdef CONFIG_LEGACY
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#define BRIDGE_ID 17
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#define VIA_ID 2
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#else
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#define BRIDGE_ID 28
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#define VIA_ID 4
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#endif
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#if defined(CONFIG_PCI)
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC2"
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#define CONFIG_TSEC4
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#define CONFIG_TSEC4_NAME "eTSEC3"
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#undef CONFIG_MPC85XX_FEC
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#define CONFIG_PHY_MARVELL
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC3_PHY_ADDR 2
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#define TSEC4_PHY_ADDR 3
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC4_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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/* Options are: eTSEC[0-3] */
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#define CONFIG_ETHPRIME "eTSEC0"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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#define CONFIG_ENV_ADDR 0xfff80000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#endif
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
|
*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Environment Configuration
|
*/
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#endif
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#define CONFIG_IPADDR 192.168.1.253
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH "/nfsroot"
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#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
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#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
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|
#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ecc=off\0" \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
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" $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
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" $filesize\0" \
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"consoledev=ttyS1\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=ramdisk.uboot\0" \
|
"fdtaddr=1e00000\0" \
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"fdtfile=mpc8548cds.dtb\0"
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
"setenv bootargs root=/dev/nfs rw " \
|
"nfsroot=$serverip:$rootpath " \
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
"tftp $loadaddr $bootfile;" \
|
"tftp $fdtaddr $fdtfile;" \
|
"bootm $loadaddr - $fdtaddr"
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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