/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
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#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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/*
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* System Clock Setup
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*/
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
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#else
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66000000
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#endif
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/*
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* Hardware Reset Configuration Word
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* if CLKIN is 66MHz, then
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* CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_1X1 |\
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HRCWL_SVCOD_DIV_2 |\
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HRCWL_CSB_TO_CLKIN_6X1 |\
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HRCWL_CORE_TO_CSB_1_5X1)
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_AGENT |\
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HRCWH_PCI1_ARBITER_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LDP_CLEAR)
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#else
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LDP_CLEAR)
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#endif
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/* Arbiter Configuration Register */
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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/* System Priority Control Register */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
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/*
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* IP blocks clock configuration
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*/
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
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#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
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/*
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* System IO Config
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*/
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#define CONFIG_SYS_SICRH 0x00000000
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#define CONFIG_SYS_SICRL 0x00000000
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/*
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* Output Buffer Impedance
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*/
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#define CONFIG_SYS_OBIR 0x31100000
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_HWCONFIG
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN)
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/* 0x80080001 */ /* ODT 150ohm on SoC */
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#undef CONFIG_DDR_ECC /* support DDR ECC function */
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#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
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#if defined(CONFIG_SPD_EEPROM)
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#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
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#else
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/*
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* Manually set up DDR parameters
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* WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
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* consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
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*/
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#define CONFIG_SYS_DDR_SIZE 512 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
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| CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
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| CSCONFIG_ROW_BIT_14 \
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| CSCONFIG_COL_BIT_10)
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/* 0x80010202 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00620802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (13 << TIMING_CFG1_REFREC_SHIFT) \
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| (3 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x3935d322 */
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (6 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x131088c8 */
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#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03E00100 */
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x1432 << SDRAM_MODE_SD_SHIFT))
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/* ODT 150ohm CL=3, AL=1 on SDRAM */
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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#endif
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/*
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* Memory test
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*/
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00140000
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_FSL_ELBC 1
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| BR_PS_16 /* 16 bit port */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xFE000FF7 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/*
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* BCSR on the Local Bus
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*/
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#define CONFIG_SYS_BCSR 0xF8000000
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/* Access window base at BCSR base */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
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| BR_PS_8 \
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| BR_MS_GPCM \
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| BR_V)
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/* 0xF8000801 */
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
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| OR_GPCM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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/* 0xFFFFE9F7 */
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/*
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* NAND Flash on the Local Bus
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BASE 0xE0600000
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
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| BR_DECC_CHK_GEN /* Use HW ECC */ \
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| BR_PS_8 /* 8 bit port */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
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| OR_FCM_BCTLD \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_RST \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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/* 0xFFFF919E */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
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#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
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#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
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#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#ifndef __ASSEMBLY__
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extern int board_pci_host_broken(void);
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#endif
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#define CONFIG_PCIE
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#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
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#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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|
/*
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* TSEC
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*/
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#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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|
/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_MII 1 /* MII PHY management */
|
#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_PHY_ADDR_SGMII 8
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#define TSEC2_PHY_ADDR_SGMII 4
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC1"
|
|
/* SERDES */
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
|
#define CONFIG_FSL_SERDES2 0xe3100
|
|
/*
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* SATA
|
*/
|
#define CONFIG_LIBATA
|
#define CONFIG_FSL_SATA
|
|
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
#define CONFIG_SATA1
|
#define CONFIG_SYS_SATA1_OFFSET 0x18000
|
#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
|
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2_OFFSET 0x19000
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#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
|
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
|
#ifdef CONFIG_FSL_SATA
|
#define CONFIG_LBA48
|
#endif
|
|
/*
|
* Environment
|
*/
|
#ifndef CONFIG_SYS_RAMBOOT
|
#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
#define CONFIG_ENV_SIZE 0x2000
|
#else
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
|
#endif
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
/*
|
* BOOTP options
|
*/
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
#define CONFIG_BOOTP_BOOTPATH
|
#define CONFIG_BOOTP_GATEWAY
|
#define CONFIG_BOOTP_HOSTNAME
|
|
/*
|
* Command line configuration.
|
*/
|
|
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
#ifdef CONFIG_MMC
|
#define CONFIG_FSL_ESDHC
|
#define CONFIG_FSL_ESDHC_PIN_MUX
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
|
#endif
|
|
/*
|
* Miscellaneous configurable options
|
*/
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
/*
|
* For booting Linux, the board info and command line data
|
* have to be in the first 256 MB of memory, since this is
|
* the maximum mapped by the Linux kernel during initialization.
|
*/
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
/*
|
* Core HID Setup
|
*/
|
#define CONFIG_SYS_HID0_INIT 0x000000000
|
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
HID0_ENABLE_INSTRUCTION_CACHE)
|
#define CONFIG_SYS_HID2 HID2_HBE
|
|
/*
|
* MMU Setup
|
*/
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
|
/* DDR: cache cacheable */
|
#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
|
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
|
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
|
| BATL_PP_RW \
|
| BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
|
| BATU_BL_256M \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
|
| BATL_PP_RW \
|
| BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
|
| BATU_BL_256M \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
|
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
|
| BATL_PP_RW \
|
| BATL_CACHEINHIBIT \
|
| BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
|
| BATU_BL_8M \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
|
/* BCSR: cache-inhibit and guarded */
|
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
|
| BATL_PP_RW \
|
| BATL_CACHEINHIBIT \
|
| BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
|
| BATU_BL_128K \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
|
| BATL_PP_RW \
|
| BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
|
| BATU_BL_32M \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
|
| BATL_PP_RW \
|
| BATL_CACHEINHIBIT \
|
| BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
|
/* Stack in dcache: cacheable, no memory coherence */
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
|
| BATU_BL_128K \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
|
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
|
#ifdef CONFIG_PCI
|
/* PCI MEM space: cacheable */
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
|
| BATL_PP_RW \
|
| BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
|
| BATU_BL_256M \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
/* PCI MMIO space: cache-inhibit and guarded */
|
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
|
| BATL_PP_RW \
|
| BATL_CACHEINHIBIT \
|
| BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
|
| BATU_BL_256M \
|
| BATU_VS \
|
| BATU_VP)
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
#else
|
#define CONFIG_SYS_IBAT6L (0)
|
#define CONFIG_SYS_IBAT6U (0)
|
#define CONFIG_SYS_IBAT7L (0)
|
#define CONFIG_SYS_IBAT7U (0)
|
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
#endif
|
|
#if defined(CONFIG_CMD_KGDB)
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
#endif
|
|
/*
|
* Environment Configuration
|
*/
|
|
#define CONFIG_ENV_OVERWRITE
|
|
#if defined(CONFIG_TSEC_ENET)
|
#define CONFIG_HAS_ETH0
|
#define CONFIG_HAS_ETH1
|
#endif
|
|
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
"netdev=eth0\0" \
|
"consoledev=ttyS0\0" \
|
"ramdiskaddr=1000000\0" \
|
"ramdiskfile=ramfs.83xx\0" \
|
"fdtaddr=780000\0" \
|
"fdtfile=mpc8379_mds.dtb\0" \
|
""
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
"setenv bootargs root=/dev/nfs rw " \
|
"nfsroot=$serverip:$rootpath " \
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
"$netdev:off " \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
"tftp $loadaddr $bootfile;" \
|
"tftp $fdtaddr $fdtfile;" \
|
"bootm $loadaddr - $fdtaddr"
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
"setenv bootargs root=/dev/ram rw " \
|
"console=$consoledev,$baudrate $othbootargs;" \
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
"tftp $loadaddr $bootfile;" \
|
"tftp $fdtaddr $fdtfile;" \
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
|
#endif /* __CONFIG_H */
|
