/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* C29XPCIE board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH
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#define CONFIG_SYS_TEXT_BASE 0x11000000
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#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
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#endif
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#ifdef CONFIG_NAND
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SPL_NAND_BOOT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_NAND_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TEXT_BASE 0xff800000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
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#endif
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_TPL_PAD_TO 0x20000
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/* High Level Configuration Options */
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#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
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#ifdef CONFIG_PCI
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#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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/*
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* PCI Windows
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, Slot 1, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "Slot 1"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#define CONFIG_SYS_MEMTEST_START 0x00200000
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/* DDR Setup */
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x50
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#define CONFIG_SYS_DDR_RAW_TIMING
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/* DDR ECC Setup*/
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#define CONFIG_DDR_ECC
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_SYS_SDRAM_SIZE 512
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* Platform SRAM setting */
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#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
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#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
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(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
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#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
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/*
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* IFC Definitions
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*/
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/* NOR Flash on IFC */
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#define CONFIG_SYS_FLASH_BASE 0xec000000
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
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/* 16Bit NOR Flash - S29GL512S10TFI01 */
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#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1A) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0x0
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/* CFI for NOR Flash */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/* NAND Flash on IFC */
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_NAND_BASE 0xff800000
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
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/* 8Bit NAND Flash - K9F1G08U0B */
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
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| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
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| CSOR_NAND_PB(128)) /*128 Pages Per Block*/
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
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FTIM0_NAND_TWP(0x0c) | \
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FTIM0_NAND_TWCHT(0x08) | \
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FTIM0_NAND_TWH(0x06))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
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FTIM1_NAND_TWBE(0x1d) | \
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FTIM1_NAND_TRR(0x08) | \
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FTIM1_NAND_TRP(0x0c))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x18))
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#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
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#define CONFIG_SYS_NAND_DDR_LAW 11
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/* Set up IFC registers for boot location NOR/NAND */
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#ifdef CONFIG_NAND
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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/* CPLD on IFC, selected by CS2 */
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#define CONFIG_SYS_CPLD_BASE 0xffdf0000
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#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
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| CONFIG_SYS_CPLD_BASE)
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#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
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#define CONFIG_SYS_CSOR2 0x0
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/* CPLD Timing parameters for IFC CS2 */
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#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
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FTIM2_GPCM_TCH(0x8) | \
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FTIM2_GPCM_TWP(0x1f))
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#define CONFIG_SYS_CS2_FTIM3 0x0
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#if defined(CONFIG_RAMBOOT_SPIFLASH)
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#endif
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
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#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
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#elif defined(CONFIG_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
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#else
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
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#define CONFIG_SYS_L2_SIZE (256 << 10)
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#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
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#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
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#endif
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#endif
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#endif
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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/* I2C EEPROM */
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/* enable read and write access to EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* eSPI - Enhanced SPI */
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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/* Default mode is RGMII mode */
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 2
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define CONFIG_ETHPRIME "eTSEC1"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_RAMBOOT_SPIFLASH)
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#elif defined(CONFIG_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
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#else
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
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#endif
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#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#endif
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#define CONFIG_LOADS_ECHO
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Environment Configuration
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*/
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#endif
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"loadaddr=1000000\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"fdtaddr=1e00000\0" \
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"fdtfile=name/of/device-tree.dtb\0" \
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"othbootargs=ramdisk_size=600000\0" \
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|
#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs; " \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
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#include <asm/fsl_secure_boot.h>
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#endif /* __CONFIG_H */
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