/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* BSC9131 RDB board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_NAND_FSL_IFC
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH
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#define CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_SYS_TEXT_BASE 0x11000000
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#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
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#endif
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#ifdef CONFIG_NAND
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_NAND_BOOT
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
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#define CONFIG_SPL_MAX_SIZE 8192
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#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
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#define CONFIG_SPL_RELOC_STACK 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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#endif
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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/* High Level Configuration Options */
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
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#if defined(CONFIG_SYS_CLK_100)
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#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
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#else
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#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
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#endif
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#define CONFIG_HWCONFIG
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* enable branch predition */
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#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x01ffffff
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/* DDR Setup */
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#undef CONFIG_SYS_DDR_RAW_TIMING
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#undef CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#ifndef __ASSEMBLY__
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extern unsigned long get_sdram_size(void);
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#endif
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#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
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#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
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#define CONFIG_SYS_DDR_TIMING_4 0x00000001
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#define CONFIG_SYS_DDR_TIMING_5 0x02401400
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#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
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#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
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#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
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#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
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#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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/* relocated CCSRBAR */
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#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
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/* CONFIG_SYS_IMMR */
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/* DSP CCSRBAR */
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#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
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#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
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/*
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* Memory map
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*
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* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
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* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
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* 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
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* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
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* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
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* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
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* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
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* 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
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* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
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* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
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*
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*/
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/*
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* IFC Definitions
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*/
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/* NAND Flash on IFC */
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#define CONFIG_SYS_NAND_BASE 0xff800000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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/* NAND Flash Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
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| FTIM0_NAND_TWP(0x05) \
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| FTIM0_NAND_TWCHT(0x02) \
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| FTIM0_NAND_TWH(0x04))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
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| FTIM1_NAND_TWBE(0x1E) \
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| FTIM1_NAND_TRR(0x07) \
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| FTIM1_NAND_TRP(0x05))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
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| FTIM2_NAND_TREH(0x04) \
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| FTIM2_NAND_TWHRE(0x11))
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#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_DDR_LAW 11
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/* Set up IFC registers for boot location NAND */
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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/* I2C EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* eSPI - Enhanced SPI */
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#ifdef CONFIG_FSL_ESPI
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#endif
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_MII /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#if defined(CONFIG_RAMBOOT_SPIFLASH)
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
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#elif defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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#ifdef CONFIG_USB_EHCI_HCD
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_HAS_FSL_DR_USB
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#endif
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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/*
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* Environment Configuration
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*/
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#endif
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#define CONFIG_HOSTNAME BSC9131rdb
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" CONFIG_UBOOTPATH "\0" \
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"loadaddr=1000000\0" \
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"bootfile=uImage\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=rootfs.ext2.gz.uboot\0" \
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"fdtaddr=1e00000\0" \
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"fdtfile=bsc9131rdb.dtb\0" \
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"bdev=sda1\0" \
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"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
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"bootm_size=0x37000000\0" \
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"othbootargs=ramdisk_size=600000 " \
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"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
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"usbext2boot=setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs; " \
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"usb start;" \
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"ext2load usb 0:4 $loadaddr $bootfile;" \
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"ext2load usb 0:4 $fdtaddr $fdtfile;" \
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"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs; " \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
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#endif /* __CONFIG_H */
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